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[DAG] SimplifySetCC - clang-format add/xor/sub with constant handling. NFC.

This commit is contained in:
Simon Pilgrim 2022-04-04 13:30:04 +01:00
parent 506ec85ba8
commit 328754474a
1 changed files with 22 additions and 26 deletions
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48
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -4642,37 +4642,33 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) {
if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
// Turn (X+C1) == C2 --> X == C2-C1
if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
return DAG.getSetCC(dl, VT, N0.getOperand(0),
DAG.getConstant(RHSC->getAPIntValue()-
LHSR->getAPIntValue(),
dl, N0.getValueType()), Cond);
}
if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse())
return DAG.getSetCC(
dl, VT, N0.getOperand(0),
DAG.getConstant(RHSC->getAPIntValue() - LHSR->getAPIntValue(),
dl, N0.getValueType()),
Cond);
// Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
if (N0.getOpcode() == ISD::XOR)
// If we know that all of the inverted bits are zero, don't bother
// performing the inversion.
if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
return
DAG.getSetCC(dl, VT, N0.getOperand(0),
DAG.getConstant(LHSR->getAPIntValue() ^
RHSC->getAPIntValue(),
dl, N0.getValueType()),
Cond);
// If we know that all of the inverted bits are zero, don't bother
// performing the inversion.
if (N0.getOpcode() == ISD::XOR &&
DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue()))
return DAG.getSetCC(
dl, VT, N0.getOperand(0),
DAG.getConstant(LHSR->getAPIntValue() ^ RHSC->getAPIntValue(),
dl, N0.getValueType()),
Cond);
}
// Turn (C1-X) == C2 --> X == C1-C2
if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
return
DAG.getSetCC(dl, VT, N0.getOperand(1),
DAG.getConstant(SUBC->getAPIntValue() -
RHSC->getAPIntValue(),
dl, N0.getValueType()),
Cond);
}
}
if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse())
return DAG.getSetCC(
dl, VT, N0.getOperand(1),
DAG.getConstant(SUBC->getAPIntValue() - RHSC->getAPIntValue(),
dl, N0.getValueType()),
Cond);
// Could RHSC fold directly into a compare?
if (RHSC->getValueType(0).getSizeInBits() <= 64)