forked from OSchip/llvm-project
Reverting to version - until problem isolated.
llvm-svn: 23622
This commit is contained in:
Jim Laskey
parent
d1a5bc8dbd
commit
327d4298e1
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@ -386,6 +386,7 @@ private:
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std::vector<NodeInfo*> Ordering; // Emit ordering of nodes
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ResourceTally<unsigned> Tally; // Resource usage tally
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unsigned NSlots; // Total latency
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std::map<SDNode *, unsigned> VRMap; // Node to VR map
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static const unsigned NotFound = ~0U; // Search marker
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public:
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@ -426,9 +427,7 @@ private:
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void IncludeNode(NodeInfo *NI);
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void VisitAll();
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void Schedule();
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void IdentifyGroups();
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void GatherSchedulingInfo();
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void PrepareNodeInfo();
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void GatherNodeInfo();
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bool isStrongDependency(NodeInfo *A, NodeInfo *B);
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bool isWeakDependency(NodeInfo *A, NodeInfo *B);
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void ScheduleBackward();
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@ -636,34 +635,28 @@ void SimpleSched::VisitAll() {
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}
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}
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/// IdentifyGroups - Put flagged nodes into groups.
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///
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void SimpleSched::IdentifyGroups() {
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/// GatherNodeInfo - Get latency and resource information about each node.
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///
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void SimpleSched::GatherNodeInfo() {
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// Allocate node information
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Info = new NodeInfo[NodeCount];
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// Get base of all nodes table
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SelectionDAG::allnodes_iterator AllNodes = DAG.allnodes_begin();
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// For each node being scheduled
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for (unsigned i = 0, N = NodeCount; i < N; i++) {
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// Get next node from DAG all nodes table
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SDNode *Node = AllNodes[i];
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// Fast reference to node schedule info
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NodeInfo* NI = &Info[i];
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SDNode *Node = NI->Node;
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// For each operand (in reverse to only look at flags)
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for (unsigned N = Node->getNumOperands(); 0 < N--;) {
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// Get operand
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SDOperand Op = Node->getOperand(N);
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// No more flags to walk
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if (Op.getValueType() != MVT::Flag) break;
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// Add to node group
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NodeGroup::Add(getNI(Op.Val), NI);
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}
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}
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}
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/// GatherSchedulingInfo - Get latency and resource information about each node.
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///
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void SimpleSched::GatherSchedulingInfo() {
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for (unsigned i = 0, N = NodeCount; i < N; i++) {
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NodeInfo* NI = &Info[i];
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SDNode *Node = NI->Node;
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MVT::ValueType VT = Node->getValueType(0);
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// Set up map
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Map[Node] = NI;
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// Set node
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NI->Node = Node;
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// Set pending visit count
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NI->setPending(Node->use_size());
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MVT::ValueType VT = Node->getValueType(0);
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if (Node->isTargetOpcode()) {
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MachineOpCode TOpc = Node->getTargetOpcode();
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// FIXME: This is an ugly (but temporary!) hack to test the scheduler
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@ -708,28 +701,21 @@ void SimpleSched::GatherSchedulingInfo() {
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// Sum up all the latencies for max tally size
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NSlots += NI->Latency;
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}
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}
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/// PrepareNodeInfo - Set up the basic minimum node info for scheduling.
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///
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void SimpleSched::PrepareNodeInfo() {
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// Allocate node information
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Info = new NodeInfo[NodeCount];
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// Get base of all nodes table
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SelectionDAG::allnodes_iterator AllNodes = DAG.allnodes_begin();
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// For each node being scheduled
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// Put flagged nodes into groups
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for (unsigned i = 0, N = NodeCount; i < N; i++) {
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// Get next node from DAG all nodes table
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SDNode *Node = AllNodes[i];
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// Fast reference to node schedule info
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NodeInfo* NI = &Info[i];
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// Set up map
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Map[Node] = NI;
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// Set node
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NI->Node = Node;
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// Set pending visit count
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NI->setPending(Node->use_size());
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SDNode *Node = NI->Node;
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// For each operand (in reverse to only look at flags)
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for (unsigned N = Node->getNumOperands(); 0 < N--;) {
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// Get operand
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SDOperand Op = Node->getOperand(N);
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// No more flags to walk
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if (Op.getValueType() != MVT::Flag) break;
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// Add to node group
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NodeGroup::Add(getNI(Op.Val), NI);
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}
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}
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}
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@ -1068,33 +1054,215 @@ void SimpleSched::EmitNode(NodeInfo *NI) {
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NI->VRBase = VRBase;
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}
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/// EmitDag - Generate machine code for an operand and needed dependencies.
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///
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unsigned SimpleSched::EmitDAG(SDOperand Op) {
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std::map<SDNode *, unsigned>::iterator OpI = VRMap.lower_bound(Op.Val);
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if (OpI != VRMap.end() && OpI->first == Op.Val)
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return OpI->second + Op.ResNo;
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unsigned &OpSlot = VRMap.insert(OpI, std::make_pair(Op.Val, 0))->second;
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unsigned ResultReg = 0;
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if (Op.isTargetOpcode()) {
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unsigned Opc = Op.getTargetOpcode();
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const TargetInstrDescriptor &II = TII.get(Opc);
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unsigned NumResults = CountResults(Op.Val);
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unsigned NodeOperands = CountOperands(Op.Val);
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unsigned NumMIOperands = NodeOperands + NumResults;
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#ifndef NDEBUG
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assert((unsigned(II.numOperands) == NumMIOperands || II.numOperands == -1)&&
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"#operands for dag node doesn't match .td file!");
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#endif
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// Create the new machine instruction.
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MachineInstr *MI = new MachineInstr(Opc, NumMIOperands, true, true);
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// Add result register values for things that are defined by this
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// instruction.
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if (NumResults) ResultReg = CreateVirtualRegisters(MI, NumResults, II);
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// If there is a token chain operand, emit it first, as a hack to get avoid
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// really bad cases.
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if (Op.getNumOperands() > NodeOperands &&
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Op.getOperand(NodeOperands).getValueType() == MVT::Other) {
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EmitDAG(Op.getOperand(NodeOperands));
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}
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// Emit all of the actual operands of this instruction, adding them to the
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// instruction as appropriate.
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for (unsigned i = 0; i != NodeOperands; ++i) {
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if (Op.getOperand(i).isTargetOpcode()) {
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// Note that this case is redundant with the final else block, but we
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// include it because it is the most common and it makes the logic
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// simpler here.
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assert(Op.getOperand(i).getValueType() != MVT::Other &&
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Op.getOperand(i).getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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unsigned VReg = EmitDAG(Op.getOperand(i));
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MI->addRegOperand(VReg, MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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assert(II.OpInfo[i+NumResults].RegClass &&
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"Don't have operand info for this instruction!");
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#ifndef NDEBUG
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if (RegMap->getRegClass(VReg) != II.OpInfo[i+NumResults].RegClass) {
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std::cerr << "OP: ";
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Op.getOperand(i).Val->dump(&DAG); std::cerr << "\nUSE: ";
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Op.Val->dump(&DAG); std::cerr << "\n";
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}
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#endif
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assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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} else if (ConstantSDNode *C =
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dyn_cast<ConstantSDNode>(Op.getOperand(i))) {
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MI->addZeroExtImm64Operand(C->getValue());
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} else if (RegisterSDNode*R =dyn_cast<RegisterSDNode>(Op.getOperand(i))) {
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MI->addRegOperand(R->getReg(), MachineOperand::Use);
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} else if (GlobalAddressSDNode *TGA =
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dyn_cast<GlobalAddressSDNode>(Op.getOperand(i))) {
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MI->addGlobalAddressOperand(TGA->getGlobal(), false, 0);
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} else if (BasicBlockSDNode *BB =
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dyn_cast<BasicBlockSDNode>(Op.getOperand(i))) {
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MI->addMachineBasicBlockOperand(BB->getBasicBlock());
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} else if (FrameIndexSDNode *FI =
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dyn_cast<FrameIndexSDNode>(Op.getOperand(i))) {
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MI->addFrameIndexOperand(FI->getIndex());
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} else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(Op.getOperand(i))) {
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unsigned Idx = ConstPool->getConstantPoolIndex(CP->get());
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MI->addConstantPoolIndexOperand(Idx);
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} else if (ExternalSymbolSDNode *ES =
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dyn_cast<ExternalSymbolSDNode>(Op.getOperand(i))) {
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MI->addExternalSymbolOperand(ES->getSymbol(), false);
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} else {
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assert(Op.getOperand(i).getValueType() != MVT::Other &&
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Op.getOperand(i).getValueType() != MVT::Flag &&
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"Chain and flag operands should occur at end of operand list!");
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unsigned VReg = EmitDAG(Op.getOperand(i));
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MI->addRegOperand(VReg, MachineOperand::Use);
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// Verify that it is right.
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assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
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assert(II.OpInfo[i+NumResults].RegClass &&
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"Don't have operand info for this instruction!");
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assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass &&
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"Register class of operand and regclass of use don't agree!");
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}
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}
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// Finally, if this node has any flag operands, we *must* emit them last, to
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// avoid emitting operations that might clobber the flags.
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if (Op.getNumOperands() > NodeOperands) {
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unsigned i = NodeOperands;
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if (Op.getOperand(i).getValueType() == MVT::Other)
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++i; // the chain is already selected.
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for (unsigned N = Op.getNumOperands(); i < N; i++) {
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assert(Op.getOperand(i).getValueType() == MVT::Flag &&
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"Must be flag operands!");
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EmitDAG(Op.getOperand(i));
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}
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}
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// Now that we have emitted all operands, emit this instruction itself.
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if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
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BB->insert(BB->end(), MI);
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} else {
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// Insert this instruction into the end of the basic block, potentially
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// taking some custom action.
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BB = DAG.getTargetLoweringInfo().InsertAtEndOfBasicBlock(MI, BB);
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}
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} else {
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switch (Op.getOpcode()) {
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default:
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Op.Val->dump();
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assert(0 && "This target-independent node should have been selected!");
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case ISD::EntryToken: break;
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case ISD::TokenFactor:
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for (unsigned i = 0, N = Op.getNumOperands(); i < N; i++) {
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EmitDAG(Op.getOperand(i));
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}
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break;
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case ISD::CopyToReg: {
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SDOperand FlagOp; FlagOp.ResNo = 0;
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if (Op.getNumOperands() == 4) {
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FlagOp = Op.getOperand(3);
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}
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if (Op.getOperand(0).Val != FlagOp.Val) {
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EmitDAG(Op.getOperand(0)); // Emit the chain.
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}
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unsigned Val = EmitDAG(Op.getOperand(2));
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if (FlagOp.Val) {
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EmitDAG(FlagOp);
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}
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MRI.copyRegToReg(*BB, BB->end(),
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cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
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RegMap->getRegClass(Val));
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break;
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}
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case ISD::CopyFromReg: {
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EmitDAG(Op.getOperand(0)); // Emit the chain.
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unsigned SrcReg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
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// Figure out the register class to create for the destreg.
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const TargetRegisterClass *TRC = 0;
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if (MRegisterInfo::isVirtualRegister(SrcReg)) {
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TRC = RegMap->getRegClass(SrcReg);
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} else {
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// Pick the register class of the right type that contains this physreg.
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for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
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E = MRI.regclass_end(); I != E; ++I)
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if ((*I)->getType() == Op.Val->getValueType(0) &&
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(*I)->contains(SrcReg)) {
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TRC = *I;
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break;
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}
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assert(TRC && "Couldn't find register class for reg copy!");
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}
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// Create the reg, emit the copy.
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ResultReg = RegMap->createVirtualRegister(TRC);
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MRI.copyRegToReg(*BB, BB->end(), ResultReg, SrcReg, TRC);
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break;
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}
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}
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}
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OpSlot = ResultReg;
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return ResultReg+Op.ResNo;
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}
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/// Schedule - Order nodes according to selected style.
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///
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void SimpleSched::Schedule() {
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// Number the nodes
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NodeCount = DAG.allnodes_size();
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// Set up minimum info for scheduling.
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PrepareNodeInfo();
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// Construct node groups for flagged nodes
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IdentifyGroups();
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// Breadth first walk of DAG
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VisitAll();
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// Don't waste time if is only entry and return
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if (ScheduleStyle != noScheduling && NodeCount > 3) {
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// Get latency and resource requirements
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GatherSchedulingInfo();
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DEBUG(dump("Pre-"));
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// Push back long instructions and critical path
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ScheduleBackward();
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DEBUG(dump("Mid-"));
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// Pack instructions to maximize resource utilization
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ScheduleForward();
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switch (ScheduleStyle) {
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case simpleScheduling:
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// Number the nodes
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NodeCount = DAG.allnodes_size();
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// Don't waste time if is only entry and return
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if (NodeCount > 3) {
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// Get latency and resource requirements
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GatherNodeInfo();
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// Breadth first walk of DAG
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VisitAll();
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DEBUG(dump("Pre-"));
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// Push back long instructions and critical path
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ScheduleBackward();
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DEBUG(dump("Mid-"));
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// Pack instructions to maximize resource utilization
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ScheduleForward();
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DEBUG(dump("Post-"));
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// Emit in scheduled order
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EmitAll();
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break;
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} // fall thru
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case noScheduling:
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// Emit instructions in using a DFS from the exit root
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EmitDAG(DAG.getRoot());
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break;
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}
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DEBUG(dump("Post-"));
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// Emit in scheduled order
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EmitAll();
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}
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/// printSI - Print schedule info.
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