forked from OSchip/llvm-project
[MIPS GlobalISel] Add lowerCall
Add minimal support to lower function calls. Support only functions with arguments/return that go through registers and have type i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D45627 llvm-svn: 334071
This commit is contained in:
Petar Jovanovic
parent
2ebe3a0240
commit
326ec32403
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@ -15,6 +15,7 @@
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#include "MipsCallLowering.h"
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#include "MipsCCState.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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using namespace llvm;
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@ -44,10 +45,25 @@ public:
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private:
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virtual void assignValueToReg(unsigned ValVReg, unsigned PhysReg) override;
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void markPhysRegUsed(unsigned PhysReg) {
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virtual void markPhysRegUsed(unsigned PhysReg) {
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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}
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};
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class CallReturnHandler : public IncomingValueHandler {
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public:
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CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder &MIB)
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: IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
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private:
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virtual void markPhysRegUsed(unsigned PhysReg) override {
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MIB.addDef(PhysReg, RegState::Implicit);
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}
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MachineInstrBuilder &MIB;
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};
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} // end anonymous namespace
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void IncomingValueHandler::assignValueToReg(unsigned ValVReg,
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@ -198,6 +214,118 @@ bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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return true;
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}
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bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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CallingConv::ID CallConv,
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const MachineOperand &Callee,
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const ArgInfo &OrigRet,
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ArrayRef<ArgInfo> OrigArgs) const {
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if (CallConv != CallingConv::C)
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return false;
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for (auto &Arg : OrigArgs) {
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if (!isSupportedType(Arg.Ty))
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return false;
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if (Arg.Flags.isByVal() || Arg.Flags.isSRet())
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return false;
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}
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if (OrigRet.Reg && !isSupportedType(OrigRet.Ty))
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return false;
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
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const MipsTargetMachine &TM =
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static_cast<const MipsTargetMachine &>(MF.getTarget());
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const MipsABIInfo &ABI = TM.getABI();
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MachineInstrBuilder CallSeqStart =
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MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
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// FIXME: Add support for pic calling sequences, long call sequences for O32,
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// N32 and N64. First handle the case when Callee.isReg().
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if (Callee.isReg())
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return false;
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MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Mips::JAL);
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MIB.addDef(Mips::SP, RegState::Implicit);
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MIB.add(Callee);
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
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TargetLowering::ArgListTy FuncOrigArgs;
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FuncOrigArgs.reserve(OrigArgs.size());
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SmallVector<ArgInfo, 8> ArgInfos;
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SmallVector<unsigned, 8> OrigArgIndices;
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unsigned i = 0;
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for (auto &Arg : OrigArgs) {
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TargetLowering::ArgListEntry Entry;
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Entry.Ty = Arg.Ty;
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FuncOrigArgs.push_back(Entry);
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splitToValueTypes(Arg, i, ArgInfos, OrigArgIndices);
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++i;
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}
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SmallVector<ISD::OutputArg, 8> Outs;
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subTargetRegTypeForCallingConv(
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MIRBuilder, ArgInfos, OrigArgIndices,
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[&](ISD::ArgFlagsTy flags, EVT vt, EVT argvt, bool used, unsigned origIdx,
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unsigned partOffs) {
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Outs.emplace_back(flags, vt, argvt, used, origIdx, partOffs);
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});
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SmallVector<CCValAssign, 8> ArgLocs;
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MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
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F.getContext());
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const char *Call = Callee.isSymbol() ? Callee.getSymbolName() : nullptr;
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CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
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OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
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if (!RetHandler.handle(ArgLocs, ArgInfos)) {
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return false;
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}
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// TODO: Calculate stack offset.
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CallSeqStart.addImm(ABI.GetCalleeAllocdArgSizeInBytes(CallConv)).addImm(0);
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MIRBuilder.insertInstr(MIB);
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if (OrigRet.Reg) {
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ArgInfos.clear();
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SmallVector<unsigned, 8> OrigRetIndices;
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splitToValueTypes(OrigRet, 0, ArgInfos, OrigRetIndices);
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SmallVector<ISD::InputArg, 8> Ins;
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subTargetRegTypeForCallingConv(
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MIRBuilder, ArgInfos, OrigRetIndices,
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[&](ISD::ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
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unsigned origIdx, unsigned partOffs) {
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Ins.emplace_back(flags, vt, argvt, used, origIdx, partOffs);
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});
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SmallVector<CCValAssign, 8> ArgLocs;
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MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
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F.getContext());
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CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), OrigRet.Ty, Call);
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CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
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if (!Handler.handle(ArgLocs, ArgInfos))
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return false;
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}
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MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP)
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.addImm(ABI.GetCalleeAllocdArgSizeInBytes(CallConv))
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.addImm(0);
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return true;
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}
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void MipsCallLowering::subTargetRegTypeForCallingConv(
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MachineIRBuilder &MIRBuilder, ArrayRef<ArgInfo> Args,
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ArrayRef<unsigned> OrigArgIndices, const FunTy &PushBack) const {
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@ -48,6 +48,10 @@ public:
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bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
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ArrayRef<unsigned> VRegs) const override;
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bool lowerCall(MachineIRBuilder &MIRBuilder, CallingConv::ID CallConv,
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const MachineOperand &Callee, const ArgInfo &OrigRet,
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ArrayRef<ArgInfo> OrigArgs) const override;
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private:
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using FunTy =
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std::function<void(ISD::ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
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@ -0,0 +1,27 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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declare i32 @f(i32 %a, i32 %b);
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define i32 @g(i32 %a0, i32 %a1, i32 %x, i32 %y) {
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; MIPS32-LABEL: name: g
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; MIPS32: bb.1.entry:
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; MIPS32: liveins: $a0, $a1, $a2, $a3
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY $a1
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; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2
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; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3
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; MIPS32: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
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; MIPS32: $a0 = COPY [[COPY2]](s32)
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; MIPS32: $a1 = COPY [[COPY3]](s32)
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; MIPS32: JAL @f, csr_o32, implicit-def $ra, implicit-def $sp, implicit $a0, implicit $a1, implicit-def $v0
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; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY $v0
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; MIPS32: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp
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; MIPS32: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY4]], [[COPY4]]
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; MIPS32: $v0 = COPY [[ADD]](s32)
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; MIPS32: RetRA implicit $v0
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entry:
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%z = call i32 @f(i32 %x, i32 %y)
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%doublez = add i32 %z, %z
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ret i32 %doublez
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}
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@ -0,0 +1,26 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
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declare i32 @f(i32 %a, i32 %b);
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define i32 @g(i32 %a0, i32 %a1, i32 %x, i32 %y) {
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; MIPS32-LABEL: g:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: addiu $sp, $sp, -24
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; MIPS32-NEXT: .cfi_def_cfa_offset 24
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; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
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; MIPS32-NEXT: .cfi_offset 31, -4
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; MIPS32-NEXT: move $4, $6
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; MIPS32-NEXT: move $5, $7
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; MIPS32-NEXT: jal f
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; MIPS32-NEXT: nop
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; MIPS32-NEXT: addu $2, $2, $2
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; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
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; MIPS32-NEXT: addiu $sp, $sp, 24
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%z = call i32 @f(i32 %x, i32 %y)
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%doublez = add i32 %z, %z
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ret i32 %doublez
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}
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