forked from OSchip/llvm-project
[ATTRIBUTE] Support base vector types of __attribute__((mode)), patch by Alexey Frolov
Base type of attribute((mode)) can actually be a vector type. The patch is to distinguish between base type and base element type. This fixes http://llvm.org/PR17453. Differential Revision: http://reviews.llvm.org/D10058 llvm-svn: 240125
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@ -2685,6 +2685,8 @@ def err_mode_not_primitive : Error<
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"mode attribute only supported for integer and floating-point types">;
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def err_mode_wrong_type : Error<
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"type of machine mode does not match type of base type">;
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def err_complex_mode_vector_type : Error<
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"type of machine mode does not support base vector types">;
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def err_attr_wrong_decl : Error<
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"%0 attribute invalid on this declaration, requires typedef or value">;
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def warn_attribute_nonnull_no_pointers : Warning<
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@ -3154,16 +3154,22 @@ static void handleModeAttr(Sema &S, Decl *D, const AttributeList &Attr) {
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return;
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}
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if (!OldTy->getAs<BuiltinType>() && !OldTy->isComplexType())
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// Base type can also be a vector type (see PR17453).
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// Distinguish between base type and base element type.
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QualType OldElemTy = OldTy;
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if (const VectorType *VT = OldTy->getAs<VectorType>())
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OldElemTy = VT->getElementType();
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if (!OldElemTy->getAs<BuiltinType>() && !OldElemTy->isComplexType())
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S.Diag(Attr.getLoc(), diag::err_mode_not_primitive);
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else if (IntegerMode) {
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if (!OldTy->isIntegralOrEnumerationType())
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if (!OldElemTy->isIntegralOrEnumerationType())
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S.Diag(Attr.getLoc(), diag::err_mode_wrong_type);
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} else if (ComplexMode) {
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if (!OldTy->isComplexType())
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if (!OldElemTy->isComplexType())
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S.Diag(Attr.getLoc(), diag::err_mode_wrong_type);
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} else {
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if (!OldTy->isFloatingType())
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if (!OldElemTy->isFloatingType())
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S.Diag(Attr.getLoc(), diag::err_mode_wrong_type);
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}
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@ -3176,21 +3182,40 @@ static void handleModeAttr(Sema &S, Decl *D, const AttributeList &Attr) {
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return;
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}
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QualType NewTy;
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QualType NewElemTy;
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if (IntegerMode)
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NewTy = S.Context.getIntTypeForBitwidth(DestWidth,
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OldTy->isSignedIntegerType());
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NewElemTy = S.Context.getIntTypeForBitwidth(
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DestWidth, OldElemTy->isSignedIntegerType());
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else
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NewTy = S.Context.getRealTypeForBitwidth(DestWidth);
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NewElemTy = S.Context.getRealTypeForBitwidth(DestWidth);
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if (NewTy.isNull()) {
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if (NewElemTy.isNull()) {
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S.Diag(Attr.getLoc(), diag::err_machine_mode) << 1 /*Unsupported*/ << Name;
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return;
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}
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if (ComplexMode) {
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NewTy = S.Context.getComplexType(NewTy);
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NewElemTy = S.Context.getComplexType(NewElemTy);
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}
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QualType NewTy = NewElemTy;
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if (const VectorType *OldVT = OldTy->getAs<VectorType>()) {
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// Complex machine mode does not support base vector types.
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if (ComplexMode) {
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S.Diag(Attr.getLoc(), diag::err_complex_mode_vector_type);
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return;
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}
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unsigned NumElements = S.Context.getTypeSize(OldElemTy) *
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OldVT->getNumElements() /
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S.Context.getTypeSize(NewElemTy);
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NewTy =
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S.Context.getVectorType(NewElemTy, NumElements, OldVT->getVectorKind());
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}
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if (NewTy.isNull()) {
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S.Diag(Attr.getLoc(), diag::err_mode_wrong_type);
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return;
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}
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// Install the new type.
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@ -0,0 +1,41 @@
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// RUN: %clang_cc1 -triple x86_64-unknown-unknown %s -emit-llvm -o - | FileCheck %s
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typedef int __attribute__((mode(byte))) __attribute__((vector_size(4))) vec_t1;
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typedef int __attribute__((mode(QI))) __attribute__((vector_size(8))) vec_t2;
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typedef int __attribute__((mode(SI))) __attribute__((vector_size(16))) vec_t3;
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typedef int __attribute__((mode(DI))) __attribute__((vector_size(64)))vec_t4;
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typedef float __attribute__((mode(SF))) __attribute__((vector_size(128))) vec_t5;
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typedef float __attribute__((mode(DF))) __attribute__((vector_size(256))) vec_t6;
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void check() {
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// CHECK: alloca <4 x i8>
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vec_t1 v1;
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// CHECK: alloca <8 x i8>
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vec_t2 v2;
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// CHECK: alloca <4 x i32>
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vec_t3 v3;
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// CHECK: alloca <8 x i64>
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vec_t4 v4;
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// CHECK: alloca <32 x float>
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vec_t5 v5;
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// CHECK: alloca <32 x double>
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vec_t6 v6;
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}
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// CHECK: ret i32 4
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int check_size1() { return sizeof(vec_t1); }
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// CHECK: ret i32 8
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int check_size2() { return sizeof(vec_t2); }
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// CHECK: ret i32 16
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int check_size3() { return sizeof(vec_t3); }
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// CHECK: ret i32 64
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int check_size4() { return sizeof(vec_t4); }
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// CHECK: ret i32 128
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int check_size5() { return sizeof(vec_t5); }
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// CHECK: ret i32 256
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int check_size6() { return sizeof(vec_t6); }
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@ -0,0 +1,26 @@
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// RUN: %clang_cc1 -fsyntax-only -verify %s
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// Correct cases.
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typedef int __attribute__((mode(byte))) __attribute__((vector_size(256))) vec_t1;
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typedef int __attribute__((mode(QI))) __attribute__((vector_size(256))) vec_t2;
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typedef int __attribute__((mode(SI))) __attribute__((vector_size(256))) vec_t3;
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typedef int __attribute__((mode(DI))) __attribute__((vector_size(256)))vec_t4;
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typedef float __attribute__((mode(SF))) __attribute__((vector_size(256))) vec_t5;
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typedef float __attribute__((mode(DF))) __attribute__((vector_size(256))) vec_t6;
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typedef float __attribute__((mode(XF))) __attribute__((vector_size(256))) vec_t7;
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// Incorrect cases.
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typedef float __attribute__((mode(QC))) __attribute__((vector_size(256))) vec_t8;
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// expected-error@-1{{unsupported machine mode 'QC'}}
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// expected-error@-2{{type of machine mode does not match type of base type}}
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typedef _Complex float __attribute__((mode(HC))) __attribute__((vector_size(256))) vec_t9;
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// expected-error@-1{{unsupported machine mode 'HC'}}
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// expected-error@-2{{invalid vector element type '_Complex float'}}
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typedef int __attribute__((mode(SC))) __attribute__((vector_size(256))) vec_t10;
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// expected-error@-1{{type of machine mode does not match type of base type}}
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// expected-error@-2{{type of machine mode does not support base vector types}}
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typedef float __attribute__((mode(DC))) __attribute__((vector_size(256))) vec_t11;
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// expected-error@-1{{type of machine mode does not match type of base type}}
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// expected-error@-2{{type of machine mode does not support base vector types}}
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typedef _Complex float __attribute__((mode(XC))) __attribute__((vector_size(256))) vec_t12;
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// expected-error@-1{{invalid vector element type '_Complex float'}}
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