forked from OSchip/llvm-project
[SelectionDAG][RISCV] Emit a canonical sign bit test from ExpandIntRes_ABS.
Instead of emitting 0 > Hi, emit Hi < 0. If Hi needs to be expanded again this will allow the special case for sign bit tests in ExpandIntOp_SETCC to trigger. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D120761
This commit is contained in:
Craig Topper
parent
a1f8349d77
commit
324c0a7206
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@ -3160,8 +3160,8 @@ void DAGTypeLegalizer::ExpandIntRes_ABS(SDNode *N, SDValue &Lo, SDValue &Hi) {
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SDValue NegLo, NegHi;
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SplitInteger(Neg, NegLo, NegHi);
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SDValue HiIsNeg = DAG.getSetCC(dl, getSetCCResultType(NVT),
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DAG.getConstant(0, dl, NVT), Hi, ISD::SETGT);
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SDValue HiIsNeg = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
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DAG.getConstant(0, dl, NVT), ISD::SETLT);
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Lo = DAG.getSelect(dl, NVT, HiIsNeg, NegLo, Lo);
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Hi = DAG.getSelect(dl, NVT, HiIsNeg, NegHi, Hi);
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}
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@ -464,17 +464,16 @@ define i128 @abs128(i128 %x) {
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; RV32I-NEXT: lw a4, 12(a1)
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; RV32I-NEXT: snez a5, a3
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; RV32I-NEXT: mv a6, a5
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; RV32I-NEXT: bnez a2, .LBB8_5
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; RV32I-NEXT: beqz a2, .LBB8_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: li a7, 0
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; RV32I-NEXT: bnez a4, .LBB8_6
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; RV32I-NEXT: snez a6, a2
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; RV32I-NEXT: .LBB8_2:
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; RV32I-NEXT: lw a1, 8(a1)
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; RV32I-NEXT: beqz a7, .LBB8_4
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; RV32I-NEXT: .LBB8_3:
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; RV32I-NEXT: bgez a4, .LBB8_4
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; RV32I-NEXT: # %bb.3:
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; RV32I-NEXT: neg a7, a1
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; RV32I-NEXT: snez a1, a1
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; RV32I-NEXT: sltu t0, a7, a6
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; RV32I-NEXT: snez a1, a1
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; RV32I-NEXT: add a1, a4, a1
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; RV32I-NEXT: add a1, a1, t0
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; RV32I-NEXT: neg a4, a1
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@ -488,15 +487,6 @@ define i128 @abs128(i128 %x) {
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; RV32I-NEXT: sw a2, 4(a0)
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; RV32I-NEXT: sw a4, 12(a0)
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB8_5:
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; RV32I-NEXT: snez a6, a2
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; RV32I-NEXT: li a7, 0
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; RV32I-NEXT: beqz a4, .LBB8_2
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; RV32I-NEXT: .LBB8_6:
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; RV32I-NEXT: slti a7, a4, 0
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; RV32I-NEXT: lw a1, 8(a1)
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; RV32I-NEXT: bnez a7, .LBB8_3
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; RV32I-NEXT: j .LBB8_4
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;
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; RV32ZBB-LABEL: abs128:
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; RV32ZBB: # %bb.0:
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@ -505,17 +495,16 @@ define i128 @abs128(i128 %x) {
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; RV32ZBB-NEXT: lw a4, 12(a1)
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; RV32ZBB-NEXT: snez a5, a3
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; RV32ZBB-NEXT: mv a6, a5
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; RV32ZBB-NEXT: bnez a2, .LBB8_5
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; RV32ZBB-NEXT: beqz a2, .LBB8_2
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; RV32ZBB-NEXT: # %bb.1:
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; RV32ZBB-NEXT: li a7, 0
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; RV32ZBB-NEXT: bnez a4, .LBB8_6
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; RV32ZBB-NEXT: snez a6, a2
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; RV32ZBB-NEXT: .LBB8_2:
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; RV32ZBB-NEXT: lw a1, 8(a1)
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; RV32ZBB-NEXT: beqz a7, .LBB8_4
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; RV32ZBB-NEXT: .LBB8_3:
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; RV32ZBB-NEXT: bgez a4, .LBB8_4
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; RV32ZBB-NEXT: # %bb.3:
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; RV32ZBB-NEXT: neg a7, a1
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; RV32ZBB-NEXT: snez a1, a1
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; RV32ZBB-NEXT: sltu t0, a7, a6
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; RV32ZBB-NEXT: snez a1, a1
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; RV32ZBB-NEXT: add a1, a4, a1
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; RV32ZBB-NEXT: add a1, a1, t0
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; RV32ZBB-NEXT: neg a4, a1
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@ -529,45 +518,35 @@ define i128 @abs128(i128 %x) {
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; RV32ZBB-NEXT: sw a2, 4(a0)
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; RV32ZBB-NEXT: sw a4, 12(a0)
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; RV32ZBB-NEXT: ret
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; RV32ZBB-NEXT: .LBB8_5:
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; RV32ZBB-NEXT: snez a6, a2
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; RV32ZBB-NEXT: li a7, 0
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; RV32ZBB-NEXT: beqz a4, .LBB8_2
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; RV32ZBB-NEXT: .LBB8_6:
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; RV32ZBB-NEXT: slti a7, a4, 0
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; RV32ZBB-NEXT: lw a1, 8(a1)
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; RV32ZBB-NEXT: bnez a7, .LBB8_3
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; RV32ZBB-NEXT: j .LBB8_4
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;
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; RV32ZBT-LABEL: abs128:
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; RV32ZBT: # %bb.0:
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; RV32ZBT-NEXT: lw a2, 12(a1)
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; RV32ZBT-NEXT: lw a3, 8(a1)
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; RV32ZBT-NEXT: lw a4, 0(a1)
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; RV32ZBT-NEXT: lw a1, 4(a1)
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; RV32ZBT-NEXT: slti a5, a2, 0
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; RV32ZBT-NEXT: cmov a5, a2, a5, zero
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; RV32ZBT-NEXT: snez a6, a4
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; RV32ZBT-NEXT: snez a7, a1
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; RV32ZBT-NEXT: cmov a7, a1, a7, a6
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; RV32ZBT-NEXT: neg t0, a3
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; RV32ZBT-NEXT: sltu t1, t0, a7
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; RV32ZBT-NEXT: snez t2, a3
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; RV32ZBT-NEXT: add t2, a2, t2
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; RV32ZBT-NEXT: add t1, t2, t1
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; RV32ZBT-NEXT: neg t1, t1
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; RV32ZBT-NEXT: cmov a2, a5, t1, a2
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; RV32ZBT-NEXT: sub a7, t0, a7
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; RV32ZBT-NEXT: cmov a3, a5, a7, a3
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; RV32ZBT-NEXT: add a6, a1, a6
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; RV32ZBT-NEXT: neg a6, a6
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; RV32ZBT-NEXT: cmov a1, a5, a6, a1
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; RV32ZBT-NEXT: neg a6, a4
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; RV32ZBT-NEXT: cmov a4, a5, a6, a4
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; RV32ZBT-NEXT: sw a4, 0(a0)
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; RV32ZBT-NEXT: sw a3, 8(a0)
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; RV32ZBT-NEXT: sw a1, 4(a0)
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; RV32ZBT-NEXT: sw a2, 12(a0)
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; RV32ZBT-NEXT: lw a2, 0(a1)
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; RV32ZBT-NEXT: lw a3, 4(a1)
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; RV32ZBT-NEXT: lw a4, 12(a1)
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; RV32ZBT-NEXT: lw a1, 8(a1)
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; RV32ZBT-NEXT: snez a5, a2
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; RV32ZBT-NEXT: snez a6, a3
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; RV32ZBT-NEXT: cmov a6, a3, a6, a5
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; RV32ZBT-NEXT: neg a7, a1
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; RV32ZBT-NEXT: sltu t0, a7, a6
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; RV32ZBT-NEXT: snez t1, a1
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; RV32ZBT-NEXT: add t1, a4, t1
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; RV32ZBT-NEXT: add t0, t1, t0
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; RV32ZBT-NEXT: neg t0, t0
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; RV32ZBT-NEXT: slti t1, a4, 0
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; RV32ZBT-NEXT: cmov a4, t1, t0, a4
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; RV32ZBT-NEXT: sub a6, a7, a6
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; RV32ZBT-NEXT: cmov a1, t1, a6, a1
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; RV32ZBT-NEXT: add a5, a3, a5
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; RV32ZBT-NEXT: neg a5, a5
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; RV32ZBT-NEXT: cmov a3, t1, a5, a3
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; RV32ZBT-NEXT: neg a5, a2
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; RV32ZBT-NEXT: cmov a2, t1, a5, a2
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; RV32ZBT-NEXT: sw a2, 0(a0)
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; RV32ZBT-NEXT: sw a1, 8(a0)
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; RV32ZBT-NEXT: sw a3, 4(a0)
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; RV32ZBT-NEXT: sw a4, 12(a0)
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; RV32ZBT-NEXT: ret
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;
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; RV64I-LABEL: abs128:
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@ -615,17 +594,16 @@ define i128 @select_abs128(i128 %x) {
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; RV32I-NEXT: lw a4, 12(a1)
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; RV32I-NEXT: snez a5, a3
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; RV32I-NEXT: mv a6, a5
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; RV32I-NEXT: bnez a2, .LBB9_5
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; RV32I-NEXT: beqz a2, .LBB9_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: li a7, 0
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; RV32I-NEXT: bnez a4, .LBB9_6
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; RV32I-NEXT: snez a6, a2
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; RV32I-NEXT: .LBB9_2:
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; RV32I-NEXT: lw a1, 8(a1)
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; RV32I-NEXT: beqz a7, .LBB9_4
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; RV32I-NEXT: .LBB9_3:
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; RV32I-NEXT: bgez a4, .LBB9_4
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; RV32I-NEXT: # %bb.3:
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; RV32I-NEXT: neg a7, a1
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; RV32I-NEXT: snez a1, a1
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; RV32I-NEXT: sltu t0, a7, a6
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; RV32I-NEXT: snez a1, a1
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; RV32I-NEXT: add a1, a4, a1
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; RV32I-NEXT: add a1, a1, t0
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; RV32I-NEXT: neg a4, a1
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@ -639,15 +617,6 @@ define i128 @select_abs128(i128 %x) {
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; RV32I-NEXT: sw a2, 4(a0)
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; RV32I-NEXT: sw a4, 12(a0)
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; RV32I-NEXT: ret
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; RV32I-NEXT: .LBB9_5:
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; RV32I-NEXT: snez a6, a2
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; RV32I-NEXT: li a7, 0
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; RV32I-NEXT: beqz a4, .LBB9_2
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; RV32I-NEXT: .LBB9_6:
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; RV32I-NEXT: slti a7, a4, 0
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; RV32I-NEXT: lw a1, 8(a1)
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; RV32I-NEXT: bnez a7, .LBB9_3
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; RV32I-NEXT: j .LBB9_4
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;
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; RV32ZBB-LABEL: select_abs128:
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; RV32ZBB: # %bb.0:
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@ -656,17 +625,16 @@ define i128 @select_abs128(i128 %x) {
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; RV32ZBB-NEXT: lw a4, 12(a1)
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; RV32ZBB-NEXT: snez a5, a3
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; RV32ZBB-NEXT: mv a6, a5
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; RV32ZBB-NEXT: bnez a2, .LBB9_5
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; RV32ZBB-NEXT: beqz a2, .LBB9_2
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; RV32ZBB-NEXT: # %bb.1:
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; RV32ZBB-NEXT: li a7, 0
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; RV32ZBB-NEXT: bnez a4, .LBB9_6
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; RV32ZBB-NEXT: snez a6, a2
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; RV32ZBB-NEXT: .LBB9_2:
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; RV32ZBB-NEXT: lw a1, 8(a1)
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; RV32ZBB-NEXT: beqz a7, .LBB9_4
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; RV32ZBB-NEXT: .LBB9_3:
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; RV32ZBB-NEXT: bgez a4, .LBB9_4
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; RV32ZBB-NEXT: # %bb.3:
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; RV32ZBB-NEXT: neg a7, a1
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; RV32ZBB-NEXT: snez a1, a1
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; RV32ZBB-NEXT: sltu t0, a7, a6
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; RV32ZBB-NEXT: snez a1, a1
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; RV32ZBB-NEXT: add a1, a4, a1
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; RV32ZBB-NEXT: add a1, a1, t0
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; RV32ZBB-NEXT: neg a4, a1
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@ -680,45 +648,35 @@ define i128 @select_abs128(i128 %x) {
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; RV32ZBB-NEXT: sw a2, 4(a0)
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; RV32ZBB-NEXT: sw a4, 12(a0)
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; RV32ZBB-NEXT: ret
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; RV32ZBB-NEXT: .LBB9_5:
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; RV32ZBB-NEXT: snez a6, a2
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; RV32ZBB-NEXT: li a7, 0
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; RV32ZBB-NEXT: beqz a4, .LBB9_2
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; RV32ZBB-NEXT: .LBB9_6:
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; RV32ZBB-NEXT: slti a7, a4, 0
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; RV32ZBB-NEXT: lw a1, 8(a1)
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; RV32ZBB-NEXT: bnez a7, .LBB9_3
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; RV32ZBB-NEXT: j .LBB9_4
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;
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; RV32ZBT-LABEL: select_abs128:
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; RV32ZBT: # %bb.0:
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; RV32ZBT-NEXT: lw a2, 12(a1)
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; RV32ZBT-NEXT: lw a3, 8(a1)
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; RV32ZBT-NEXT: lw a4, 0(a1)
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; RV32ZBT-NEXT: lw a1, 4(a1)
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; RV32ZBT-NEXT: slti a5, a2, 0
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; RV32ZBT-NEXT: cmov a5, a2, a5, zero
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; RV32ZBT-NEXT: snez a6, a4
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; RV32ZBT-NEXT: snez a7, a1
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; RV32ZBT-NEXT: cmov a7, a1, a7, a6
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; RV32ZBT-NEXT: neg t0, a3
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; RV32ZBT-NEXT: sltu t1, t0, a7
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; RV32ZBT-NEXT: snez t2, a3
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; RV32ZBT-NEXT: add t2, a2, t2
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; RV32ZBT-NEXT: add t1, t2, t1
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; RV32ZBT-NEXT: neg t1, t1
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; RV32ZBT-NEXT: cmov a2, a5, t1, a2
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; RV32ZBT-NEXT: sub a7, t0, a7
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; RV32ZBT-NEXT: cmov a3, a5, a7, a3
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; RV32ZBT-NEXT: add a6, a1, a6
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; RV32ZBT-NEXT: neg a6, a6
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; RV32ZBT-NEXT: cmov a1, a5, a6, a1
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; RV32ZBT-NEXT: neg a6, a4
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; RV32ZBT-NEXT: cmov a4, a5, a6, a4
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; RV32ZBT-NEXT: sw a4, 0(a0)
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; RV32ZBT-NEXT: sw a3, 8(a0)
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; RV32ZBT-NEXT: sw a1, 4(a0)
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; RV32ZBT-NEXT: sw a2, 12(a0)
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; RV32ZBT-NEXT: lw a2, 0(a1)
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; RV32ZBT-NEXT: lw a3, 4(a1)
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; RV32ZBT-NEXT: lw a4, 12(a1)
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; RV32ZBT-NEXT: lw a1, 8(a1)
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; RV32ZBT-NEXT: snez a5, a2
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; RV32ZBT-NEXT: snez a6, a3
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; RV32ZBT-NEXT: cmov a6, a3, a6, a5
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; RV32ZBT-NEXT: neg a7, a1
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; RV32ZBT-NEXT: sltu t0, a7, a6
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; RV32ZBT-NEXT: snez t1, a1
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; RV32ZBT-NEXT: add t1, a4, t1
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; RV32ZBT-NEXT: add t0, t1, t0
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; RV32ZBT-NEXT: neg t0, t0
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; RV32ZBT-NEXT: slti t1, a4, 0
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; RV32ZBT-NEXT: cmov a4, t1, t0, a4
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; RV32ZBT-NEXT: sub a6, a7, a6
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; RV32ZBT-NEXT: cmov a1, t1, a6, a1
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; RV32ZBT-NEXT: add a5, a3, a5
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; RV32ZBT-NEXT: neg a5, a5
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; RV32ZBT-NEXT: cmov a3, t1, a5, a3
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; RV32ZBT-NEXT: neg a5, a2
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; RV32ZBT-NEXT: cmov a2, t1, a5, a2
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; RV32ZBT-NEXT: sw a2, 0(a0)
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; RV32ZBT-NEXT: sw a1, 8(a0)
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; RV32ZBT-NEXT: sw a3, 4(a0)
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; RV32ZBT-NEXT: sw a4, 12(a0)
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; RV32ZBT-NEXT: ret
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;
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; RV64I-LABEL: select_abs128:
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