forked from OSchip/llvm-project
Add some crude itin approximation for VFP load / stores on A9
llvm-svn: 100671
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@ -804,6 +804,60 @@ def CortexA9Itineraries : ProcessorItineraries<[
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InstrStage<2, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [1, 1, 1]>,
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//
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// Single-precision FP Load
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// use FU_Issue to enforce the 1 load/store per cycle limit
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InstrItinData<IIC_fpLoad32, [InstrStage<1, [FU_DRegsVFP], 0, Required>,
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InstrStage<2, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0], 0>,
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InstrStage<1, [FU_NPipe]>]>,
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//
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// Double-precision FP Load
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// use FU_Issue to enforce the 1 load/store per cycle limit
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InstrItinData<IIC_fpLoad64, [InstrStage<1, [FU_DRegsVFP], 0, Required>,
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InstrStage<2, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0], 0>,
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InstrStage<1, [FU_NPipe]>]>,
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//
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// FP Load Multiple
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// use FU_Issue to enforce the 1 load/store per cycle limit
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InstrItinData<IIC_fpLoadm, [InstrStage<1, [FU_DRegsVFP], 0, Required>,
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InstrStage<2, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0], 0>,
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InstrStage<1, [FU_NPipe]>]>,
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//
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// Single-precision FP Store
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// use FU_Issue to enforce the 1 load/store per cycle limit
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InstrItinData<IIC_fpStore32,[InstrStage<1, [FU_DRegsVFP], 0, Required>,
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InstrStage<2, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0], 0>,
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InstrStage<1, [FU_NPipe]>]>,
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//
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// Double-precision FP Store
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// use FU_Issue to enforce the 1 load/store per cycle limit
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InstrItinData<IIC_fpStore64,[InstrStage<1, [FU_DRegsVFP], 0, Required>,
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InstrStage<2, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0], 0>,
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InstrStage<1, [FU_NPipe]>]>,
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//
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// FP Store Multiple
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// use FU_Issue to enforce the 1 load/store per cycle limit
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InstrItinData<IIC_fpStorem, [InstrStage<1, [FU_DRegsVFP], 0, Required>,
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InstrStage<2, [FU_DRegsN], 0, Reserved>,
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InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0], 0>,
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InstrStage<1, [FU_NPipe]>]>,
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// NEON
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// Issue through integer pipeline, and execute in NEON unit.
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// FIXME: Neon pipeline and LdSt unit are multiplexed.
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