forked from OSchip/llvm-project
Fix PR12359
- In addition to undefined, if V2 is zero vector, skip 2nd PSHUFB and POR as well as PSHUFB will zero elements with negative indices. Patch by Sriram Murali <sriram.murali@intel.com> llvm-svn: 163018
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@ -5881,8 +5881,6 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
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DebugLoc dl = SVOp->getDebugLoc();
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ArrayRef<int> MaskVals = SVOp->getMask();
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bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
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// If we have SSSE3, case 1 is generated when all result bytes come from
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// one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
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// present, fall back to case 3.
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@ -5906,7 +5904,11 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
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V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
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DAG.getNode(ISD::BUILD_VECTOR, dl,
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MVT::v16i8, &pshufbMask[0], 16));
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if (V2IsUndef)
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// As PSHUFB will zero elements with negative indices, it's safe to ignore
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// the 2nd operand if it's undefined or zero.
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if (V2.getOpcode() == ISD::UNDEF ||
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ISD::isBuildVectorAllZeros(V2.getNode()))
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return V1;
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// Calculate the shuffle mask for the second input, shuffle it, and
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@ -0,0 +1,10 @@
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; RUN: llc -asm-verbose -mtriple=x86_64-unknown-unknown -mcpu=corei7 < %s | FileCheck %s
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define <16 x i8> @shuf(<16 x i8> %inval1) {
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entry:
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%0 = shufflevector <16 x i8> %inval1, <16 x i8> zeroinitializer, <16 x i32> <i32 0, i32 4, i32 3, i32 2, i32 16, i32 16, i32 3, i32 4, i32 0, i32 4, i32 3, i32 2, i32 16, i32 16, i32 3, i32 4>
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ret <16 x i8> %0
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; CHECK: shuf
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: ret
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}
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