From 3217ca0863681c5e73e1e0f19e9de350249c45b8 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Wed, 13 Apr 2022 17:39:04 -0400
Subject: [PATCH] llvm-reduce: Copy register allocation hints to clone

---
 .../llvm-reduce/mir/preserve-reg-hints.mir    | 34 +++++++++++++++++++
 llvm/tools/llvm-reduce/ReducerWorkItem.cpp    | 13 +++++++
 2 files changed, 47 insertions(+)
 create mode 100644 llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir

diff --git a/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir b/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
new file mode 100644
index 000000000000..72dd027c45e2
--- /dev/null
+++ b/llvm/test/tools/llvm-reduce/mir/preserve-reg-hints.mir
@@ -0,0 +1,34 @@
+# REQUIRES: amdgpu-registered-target
+# RUN: llvm-reduce -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
+# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t
+
+# CHECK-INTERESTINGNESS: S_NOP 0
+
+# Make sure that register hints are preserved in the cloned function.
+
+# RESULT: registers:
+# RESULT-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
+# RESULT-NEXT: - { id: 1, class: vgpr_32, preferred-register: '' }
+# RESULT-NEXT: - { id: 2, class: vgpr_32, preferred-register: '%1' }
+# RESULT-NEXT: - { id: 3, class: vgpr_32, preferred-register: '%4' }
+# RESULT-NEXT: - { id: 4, class: vgpr_32, preferred-register: '%3' }
+---
+name: register_hints
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: vgpr_32, preferred-register: '$vgpr0' }
+  - { id: 1, class: vgpr_32, preferred-register: '' }
+  - { id: 2, class: vgpr_32, preferred-register: '%1' }
+  - { id: 3, class: vgpr_32, preferred-register: '%4' }
+  - { id: 4, class: vgpr_32, preferred-register: '%3' }
+body:             |
+  bb.0:
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    S_NOP 0
+    S_ENDPGM 0, implicit %0, implicit %1, implicit %2, implicit %3, implicit %4
+
+...
diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
index 66fe653af518..abfb82a31f91 100644
--- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
+++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp
@@ -57,6 +57,19 @@ static std::unique_ptr<MachineFunction> cloneMF(MachineFunction *SrcMF) {
     }
   }
 
+  // Copy register allocation hints.
+  for (std::pair<Register, Register> RegMapEntry : Src2DstReg) {
+    const auto &Hints = SrcMRI->getRegAllocationHints(RegMapEntry.first);
+    for (Register PrefReg : Hints.second) {
+      if (PrefReg.isVirtual()) {
+        auto PrefRegEntry = Src2DstReg.find(PrefReg);
+        assert(PrefRegEntry !=Src2DstReg.end());
+        DstMRI->addRegAllocationHint(RegMapEntry.second, PrefRegEntry->second);
+      } else
+        DstMRI->addRegAllocationHint(RegMapEntry.second, PrefReg);
+    }
+  }
+
   // Clone blocks.
   for (auto &SrcMBB : *SrcMF)
     Src2DstMBB[&SrcMBB] = DstMF->CreateMachineBasicBlock();