forked from OSchip/llvm-project
[globalisel][tablegen] Post-commit review nits for r306388. NFC
One early exit and a missing assert string. llvm-svn: 306552
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@ -1891,45 +1891,39 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
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if (!Dst->getChild(0)->isLeaf())
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return failedImport("EXTRACT_SUBREG child #1 is not a leaf");
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if (DefInit *SubRegInit =
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dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue())) {
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// Constrain the result to the same register bank as the operand.
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Record *DstIOpRec =
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getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
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DefInit *SubRegInit = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue());
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if (!SubRegInit)
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return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");
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if (DstIOpRec == nullptr)
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return failedImport("EXTRACT_SUBREG operand #1 isn't a register class");
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// Constrain the result to the same register bank as the operand.
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Record *DstIOpRec =
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getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
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CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
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CodeGenRegisterClass *SrcRC = CGRegs.getRegClass(
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getInitValueAsRegClass(Dst->getChild(0)->getLeafValue()));
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if (DstIOpRec == nullptr)
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return failedImport("EXTRACT_SUBREG operand #1 isn't a register class");
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// It would be nice to leave this constraint implicit but we're required
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// to pick a register class so constrain the result to a register class
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// that can hold the correct MVT.
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//
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// FIXME: This may introduce an extra copy if the chosen class doesn't
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// actually contain the subregisters.
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assert(Src->getExtTypes().size() == 1);
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CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
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CodeGenRegisterClass *SrcRC = CGRegs.getRegClass(
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getInitValueAsRegClass(Dst->getChild(0)->getLeafValue()));
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const auto &SrcRCDstRCPair =
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SrcRC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx);
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assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
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M.addAction<ConstrainOperandToRegClassAction>("NewI", 0,
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*SrcRCDstRCPair->second);
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M.addAction<ConstrainOperandToRegClassAction>("NewI", 1,
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*SrcRCDstRCPair->first);
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// It would be nice to leave this constraint implicit but we're required
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// to pick a register class so constrain the result to a register class
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// that can hold the correct MVT.
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//
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// FIXME: This may introduce an extra copy if the chosen class doesn't
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// actually contain the subregisters.
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assert(Src->getExtTypes().size() == 1 &&
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"Expected Src of EXTRACT_SUBREG to have one result type");
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// We're done with this pattern! It's eligible for GISel emission; return
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// it.
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++NumPatternImported;
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return std::move(M);
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}
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return failedImport("EXTRACT_SUBREG child #1 is not a subreg index");
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}
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M.addAction<ConstrainOperandsToDefinitionAction>("NewI");
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const auto &SrcRCDstRCPair =
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SrcRC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx);
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assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
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M.addAction<ConstrainOperandToRegClassAction>("NewI", 0,
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*SrcRCDstRCPair->second);
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M.addAction<ConstrainOperandToRegClassAction>("NewI", 1,
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*SrcRCDstRCPair->first);
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} else
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M.addAction<ConstrainOperandsToDefinitionAction>("NewI");
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// We're done with this pattern! It's eligible for GISel emission; return it.
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++NumPatternImported;
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