forked from OSchip/llvm-project
Add code to emulate VLD1 (multiple single elements) ARM instruction.
llvm-svn: 128637
This commit is contained in:
Caroline Tice
parent
890477f333
commit
31d8498f6f
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@ -11013,7 +11013,174 @@ EmulateInstructionARM::EmulateVSTR (const uint32_t opcode, ARMEncoding encoding)
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}
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return true;
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}
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// A8.6.307 VLDI1 (multiple single elements)
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// This instruction loads elements from memory into one, two, three or four registers, without de-interleaving. Every
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// element of each register is loaded.
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bool
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EmulateInstructionARM::EmulateVLD1Multiple (const uint32_t opcode, ARMEncoding encoding)
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{
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#if 0
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if ConditionPassed() then
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EncodingSpecificOperations(); CheckAdvSIMDEnabled(); NullCheckIfThumbEE(n);
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address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
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if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
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for r = 0 to regs-1
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for e = 0 to elements-1
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Elem[D[d+r],e,esize] = MemU[address,ebytes];
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address = address + ebytes;
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#endif
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bool success = false;
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if (ConditionPassed (opcode))
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{
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uint32_t regs;
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uint32_t alignment;
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uint32_t ebytes;
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uint32_t esize;
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uint32_t elements;
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uint32_t d;
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uint32_t n;
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uint32_t m;
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bool wback;
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bool register_index;
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switch (encoding)
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{
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case eEncodingT1:
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case eEncodingA1:
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{
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// case type of
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// when ‘0111’
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// regs = 1; if align<1> == ‘1’ then UNDEFINED;
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// when ‘1010’
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// regs = 2; if align == ‘11’ then UNDEFINED;
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// when ‘0110’
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// regs = 3; if align<1> == ‘1’ then UNDEFINED;
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// when ‘0010’
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// regs = 4;
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// otherwise
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// SEE “Related encodings”;
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uint32_t type = Bits32 (opcode, 11, 8);
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uint32_t align = Bits32 (opcode, 5, 4);
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if (type == 7) // '0111'
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{
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regs = 1;
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if (BitIsSet (align, 1))
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return false;
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}
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else if (type == 10) // '1010'
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{
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regs = 2;
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if (align == 3)
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return false;
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}
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else if (type == 6) // '0110'
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{
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regs = 3;
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if (BitIsSet (align, 1))
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return false;
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}
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else if (type == 2) // '0010'
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{
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regs = 4;
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}
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else
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return false;
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// alignment = if align == ‘00’ then 1 else 4 << UInt(align);
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if (align == 0)
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alignment = 1;
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else
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alignment = 4 << align;
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// ebytes = 1 << UInt(size); esize = 8 * ebytes; elements = 8 DIV ebytes;
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ebytes = 1 << Bits32 (opcode, 7, 6);
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esize = 8 * ebytes;
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elements = 8 / ebytes;
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// d = UInt(D:Vd); n = UInt(Rn); m = UInt(Rm);
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d = (Bit32 (opcode, 22) << 4) | Bits32 (opcode, 15, 12);
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n = Bits32 (opcode, 19, 15);
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m = Bits32 (opcode, 3, 0);
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// wback = (m != 15); register_index = (m != 15 && m != 13);
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wback = (m != 15);
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register_index = ((m != 15) && (m != 13));
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// if d+regs > 32 then UNPREDICTABLE;
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if ((d + regs) > 32)
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return false;
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}
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break;
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default:
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return false;
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}
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Register base_reg;
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base_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + n);
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uint32_t Rn = ReadCoreReg (n, &success);
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if (!success)
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return false;
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// address = R[n]; if (address MOD alignment) != 0 then GenerateAlignmentException();
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addr_t address = Rn;
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if ((address % alignment) != 0)
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return false;
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EmulateInstruction::Context context;
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// if wback then R[n] = R[n] + (if register_index then R[m] else 8*regs);
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if (wback)
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{
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uint32_t Rm = ReadCoreReg (m, &success);
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if (!success)
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return false;
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uint32_t offset;
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if (register_index)
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offset = Rm;
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else
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offset = 8 * regs;
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uint32_t value = Rn + offset;
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context.type = eContextAdjustBaseRegister;
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context.SetRegisterPlusOffset (base_reg, offset);
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_r0 + n, value))
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return false;
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}
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// for r = 0 to regs-1
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for (int r = 0; r < regs; ++r)
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{
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// for e = 0 to elements-1
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uint64_t assembled_data = 0;
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for (int e = 0; e < elements; ++e)
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{
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// Elem[D[d+r],e,esize] = MemU[address,ebytes];
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context.type = eContextRegisterLoad;
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context.SetRegisterPlusOffset (base_reg, address - Rn);
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uint64_t data = MemURead (context, address, ebytes, 0, &success);
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if (!success)
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return false;
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assembled_data = (data << (e * esize)) | assembled_data; // New data goes to the left of existing data
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// address = address + ebytes;
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address = address + ebytes;
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}
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, dwarf_d0 + d + r, assembled_data))
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return false;
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}
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}
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return true;
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}
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EmulateInstructionARM::ARMOpcode*
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EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
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{
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@ -11193,10 +11360,11 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode)
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{ 0x0e5000f0, 0x001000f0, ARMvAll, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,+/-<Rm>]{!}" },
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{ 0x0e5000f0, 0x004000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt>, <Rt2>, [<Rn>,#+/-<imm8>]!"},
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{ 0x0e500ff0, 0x000000d0, ARMV5TE_ABOVE, eEncodingA1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDRegister, "ldrd<c> <Rt>, <Rt2>, [<Rn>, +/-<Rm>]{!}"},
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{ 0x0e100f00, 0x0c100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
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{ 0x0e100f00, 0x0c100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
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{ 0x0f300f00, 0x0d100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
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{ 0x0f300f00, 0x0d100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, [<Rn>{,#+/-<imm>}]"},
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{ 0x0e100f00, 0x0c100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
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{ 0x0e100f00, 0x0c100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
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{ 0x0f300f00, 0x0d100b00, ARMvAll, eEncodingA1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
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{ 0x0f300f00, 0x0d100a00, ARMvAll, eEncodingA2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, [<Rn>{,#+/-<imm>}]"},
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{ 0xffb00000, 0xf4200000, ARMvAll, eEncodingA1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Multiple, "vld1<c>.<size> <list>, [<Rn{@<align>}],<RM>"},
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//----------------------------------------------------------------------
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// Store instructions
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@ -11488,10 +11656,11 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode)
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{ 0xfffffe00, 0x00005e00, ARMV4T_ABOVE, eEncodingT1, No_VFP, eSize16, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c> <Rt>,[<Rn>,<Rm>]" },
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{ 0xfff00fc0, 0xf9300000, ARMV6T2_ABOVE, eEncodingT2, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRSHRegister, "ldrsh<c>.w <Rt>,[<Rn>,<Rm>{,LSL #<imm2>}]" },
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{ 0xfe500000, 0xe8500000, ARMV6T2_ABOVE, eEncodingT1, No_VFP, eSize32, &EmulateInstructionARM::EmulateLDRDImmediate, "ldrd<c> <Rt?, <Rt2>, [<Rn>,#+/-<imm>]!"},
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{ 0xfe100f00, 0xec100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
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{ 0xfe100f00, 0xec100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>" },
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{ 0xffe00f00, 0xed100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
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{ 0xff300f00, 0xed100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, {<Rn>{,#+/-<imm>}]"},
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{ 0xfe100f00, 0xec100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>"},
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{ 0xfe100f00, 0xec100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDM, "vldm{mode}<c> <Rn>{!}, <list>" },
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{ 0xffe00f00, 0xed100b00, ARMvAll, eEncodingT1, VFPv2_ABOVE, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Dd>, [<Rn>{,#+/-<imm>}]"},
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{ 0xff300f00, 0xed100a00, ARMvAll, eEncodingT2, VFPv2v3, eSize32, &EmulateInstructionARM::EmulateVLDR, "vldr<c> <Sd>, {<Rn>{,#+/-<imm>}]"},
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{ 0xffb00000, 0xf9200000, ARMvAll, eEncodingT1, AdvancedSIMD, eSize32, &EmulateInstructionARM::EmulateVLD1Multiple, "vld<c>.<size> <list>, [<Rn>{@<align>}],<Rm>"},
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//----------------------------------------------------------------------
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// Store instructions
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