From 3149ec07c0247397f7d963ccff28773a00bcdf9c Mon Sep 17 00:00:00 2001 From: Jessica Clarke Date: Thu, 20 Aug 2020 18:36:50 +0100 Subject: [PATCH] [RISCV] Enable MCCodeEmitter instruction predicate verifier This ensures that we never encode an instruction which is unavailable, such as if we explicitly insert a forbidden instruction when lowering. This is particularly important on RISC-V given its high degree of modularity, and will become increasingly important as new standard extensions appear. Reviewed By: asb, lenary Differential Revision: https://reviews.llvm.org/D85015 --- .../Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp index 816206c477df..5898149c9fe1 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -84,6 +84,12 @@ public: unsigned getVMaskReg(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + +private: + FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) const; + void + verifyInstructionPredicates(const MCInst &MI, + const FeatureBitset &AvailableFeatures) const; }; } // end anonymous namespace @@ -185,6 +191,9 @@ void RISCVMCCodeEmitter::expandAddTPRel(const MCInst &MI, raw_ostream &OS, void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { + verifyInstructionPredicates(MI, + computeAvailableFeatures(STI.getFeatureBits())); + const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); // Get byte count of instruction. unsigned Size = Desc.getSize(); @@ -397,4 +406,5 @@ unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo, } } +#define ENABLE_INSTR_PREDICATE_VERIFIER #include "RISCVGenMCCodeEmitter.inc"