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[AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension 

This adds support for the v8.7-A LD64B/ST64B Accelerator extension
through a subtarget feature called "ls64". It adds four 64-byte
load/store instructions with an operand in the new GPR64x8 register
class, and one system register that's part of the same extension.

Based on patches written by Simon Tatham.

Reviewed By: ostannard

Differential Revision: https://reviews.llvm.org/D91775
This commit is contained in:
Lucas Prates 2020-11-16 14:23:14 +00:00
parent 97c006aabb
commit 313889191e
8 changed files with 126 additions and 0 deletions
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3
llvm/lib/Target/AArch64/AArch64.td
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@ -409,6 +409,9 @@ def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
def FeatureHCX : SubtargetFeature<
"hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
"true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
"true", "Enable fine grained virtualization traps extension">;

29
llvm/lib/Target/AArch64/AArch64InstrFormats.td
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@ -11255,6 +11255,35 @@ multiclass STOPregister<string asm, string instr> {
!cast<Instruction>(instr # "X")>;
}
class LoadStore64B_base<bits<3> opc, string asm_inst, string asm_ops,
dag iops, dag oops, list<dag> pat>
: I<oops, iops, asm_inst, asm_ops, "", pat>,
Sched<[]> /* FIXME: fill in scheduling details once known */ {
bits<5> Rt;
bits<5> Rn;
let Inst{31-21} = 0b11111000001;
let Inst{15} = 1;
let Inst{14-12} = opc;
let Inst{11-10} = 0b00;
let Inst{9-5} = Rn;
let Inst{4-0} = Rt;
let Predicates = [HasV8_7a];
}
class LoadStore64B<bits<3> opc, string asm_inst, dag iops, dag oops,
list<dag> pat = []>
: LoadStore64B_base<opc, asm_inst, "\t$Rt, [$Rn]", iops, oops, pat> {
let Inst{20-16} = 0b11111;
}
class Store64BV<bits<3> opc, string asm_inst, list<dag> pat = []>
: LoadStore64B_base<opc, asm_inst, "\t$Rs, $Rt, [$Rn]",
(ins GPR64x8:$Rt, GPR64sp:$Rn), (outs GPR64:$Rs), pat> {
bits<5> Rs;
let Inst{20-16} = Rs;
}
//----------------------------------------------------------------------------
// Allow the size specifier tokens to be upper case, not just lower.
def : TokenAlias<".4B", ".4b">; // Add dot product

11
llvm/lib/Target/AArch64/AArch64InstrInfo.td
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@ -155,6 +155,8 @@ def HasXS : Predicate<"Subtarget->hasXS()">,
AssemblerPredicate<(all_of FeatureXS), "xs">;
def HasWFxT : Predicate<"Subtarget->hasWFxT()">,
AssemblerPredicate<(all_of FeatureWFxT), "wfxt">;
def HasLS64 : Predicate<"Subtarget->hasLS64()">,
AssemblerPredicate<(all_of FeatureLS64), "ls64">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
@ -7745,6 +7747,15 @@ let AddedComplexity = 10 in {
// FIXME: add SVE dot-product patterns.
}
let Predicates = [HasLS64] in {
def LD64B: LoadStore64B<0b101, "ld64b", (ins GPR64sp:$Rn),
(outs GPR64x8:$Rt)>;
def ST64B: LoadStore64B<0b001, "st64b", (ins GPR64sp:$Rn, GPR64x8:$Rt),
(outs)>;
def ST64BV: Store64BV<0b011, "st64bv">;
def ST64BV0: Store64BV<0b010, "st64bv0">;
}
include "AArch64InstrAtomics.td"
include "AArch64SVEInstrInfo.td"

2
llvm/lib/Target/AArch64/AArch64Subtarget.h
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@ -172,6 +172,7 @@ protected:
bool HasXS = false;
bool HasWFxT = false;
bool HasHCX = false;
bool HasLS64 = false;
// Arm SVE2 extensions
bool HasSVE2 = false;
@ -503,6 +504,7 @@ public:
bool hasXS() const { return HasXS; }
bool hasWFxT() const { return HasWFxT; }
bool hasHCX() const { return HasHCX; }
bool hasLS64() const { return HasLS64; }
bool hasSEL2() const { return HasSEL2; }
bool hasPMU() const { return HasPMU; }
bool hasTLB_RMI() const { return HasTLB_RMI; }

4
llvm/lib/Target/AArch64/AArch64SystemOperands.td
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@ -1570,6 +1570,10 @@ def : RWSysReg<"CNTPCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b101>;
def : RWSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>;
}
// v8.7a LD64B/ST64B Accelerator Extension system register
let Requires = [{ {AArch64::FeatureLS64} }] in
def : RWSysReg<"ACCDATA_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b101>;
// Cyclone specific system registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::ProcAppleA7} }] in

1
llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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@ -473,6 +473,7 @@ static const unsigned GPR64x8DecoderTable[] = {
AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
AArch64::X20_X21_X22_X23_X24_X25_X26_X27,
AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
};
static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst,

38
llvm/test/MC/AArch64/armv8.7a-ls64.s Normal file
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@ -0,0 +1,38 @@
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ls64 < %s 2>%t | FileCheck %s
// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-LS64-ERR %s < %t
// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-NO-LS64-ERR %s < %t
ld64b x0, [x13]
st64b x14, [x13]
st64bv x1, x20, [x13]
st64bv0 x1, x22, [x13]
// CHECK: ld64b x0, [x13] // encoding: [0xa0,0xd1,0x3f,0xf8]
// CHECK: st64b x14, [x13] // encoding: [0xae,0x91,0x3f,0xf8]
// CHECK: st64bv x1, x20, [x13] // encoding: [0xb4,0xb1,0x21,0xf8]
// CHECK: st64bv0 x1, x22, [x13] // encoding: [0xb6,0xa1,0x21,0xf8]
// CHECK-NO-LS64-ERR: [[@LINE-8]]:3: error: instruction requires: ls64
// CHECK-NO-LS64-ERR: [[@LINE-8]]:3: error: instruction requires: ls64
// CHECK-NO-LS64-ERR: [[@LINE-8]]:3: error: instruction requires: ls64
// CHECK-NO-LS64-ERR: [[@LINE-8]]:3: error: instruction requires: ls64
ld64b x0, [sp]
st64b x14, [sp]
st64bv x1, x20, [sp]
st64bv0 x1, x22, [sp]
// CHECK: ld64b x0, [sp] // encoding: [0xe0,0xd3,0x3f,0xf8]
// CHECK: st64b x14, [sp] // encoding: [0xee,0x93,0x3f,0xf8]
// CHECK: st64bv x1, x20, [sp] // encoding: [0xf4,0xb3,0x21,0xf8]
// CHECK: st64bv0 x1, x22, [sp] // encoding: [0xf6,0xa3,0x21,0xf8]
ld64b x1, [x13]
ld64b x24, [x13]
// CHECK-ERR: [[@LINE-2]]:9: error: expected an even-numbered x-register in the range [x0,x22]
// CHECK-ERR: [[@LINE-2]]:9: error: expected an even-numbered x-register in the range [x0,x22]
mrs x0, accdata_el1
msr accdata_el1, x0
// CHECK: mrs x0, ACCDATA_EL1 // encoding: [0xa0,0xd0,0x38,0xd5]
// CHECK: msr ACCDATA_EL1, x0 // encoding: [0xa0,0xd0,0x18,0xd5]
// CHECK-NO-LS64-ERR: [[@LINE-4]]:11: error: expected readable system register
// CHECK-NO-LS64-ERR: [[@LINE-4]]:7: error: expected writable system register

38
llvm/test/MC/Disassembler/AArch64/armv8.7a-ls64.txt Normal file
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@ -0,0 +1,38 @@
# RUN: not llvm-mc -triple=aarch64 -mattr=+ls64 -disassemble %s 2> %t | FileCheck %s
# RUN: FileCheck --check-prefix=CHECK-ERR %s < %t
# RUN: not llvm-mc -triple=aarch64 -disassemble %s 2> %t | FileCheck --check-prefix=CHECK-NO-LS64 %s
# RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-NO-LS64-ERR %s < %t
[0xa0,0xd1,0x3f,0xf8]
[0xae,0x91,0x3f,0xf8]
[0xb4,0xb1,0x21,0xf8]
[0xb6,0xa1,0x21,0xf8]
# CHECK: ld64b x0, [x13]
# CHECK: st64b x14, [x13]
# CHECK: st64bv x1, x20, [x13]
# CHECK: st64bv0 x1, x22, [x13]
# CHECK-NO-LS64-ERR: [[@LINE-8]]:2: warning: invalid instruction encoding
# CHECK-NO-LS64-ERR: [[@LINE-8]]:2: warning: invalid instruction encoding
# CHECK-NO-LS64-ERR: [[@LINE-8]]:2: warning: invalid instruction encoding
# CHECK-NO-LS64-ERR: [[@LINE-8]]:2: warning: invalid instruction encoding
[0xe0,0xd3,0x3f,0xf8]
[0xee,0x93,0x3f,0xf8]
[0xf4,0xb3,0x21,0xf8]
[0xf6,0xa3,0x21,0xf8]
# CHECK: ld64b x0, [sp]
# CHECK: st64b x14, [sp]
# CHECK: st64bv x1, x20, [sp]
# CHECK: st64bv0 x1, x22, [sp]
[0xb3,0xd1,0x3f,0xf8]
[0xb8,0xd1,0x3f,0xf8]
# CHECK-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
# CHECK-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
[0xa0,0xd0,0x38,0xd5]
[0xa0,0xd0,0x18,0xd5]
# CHECK: mrs x0, ACCDATA_EL1
# CHECK: msr ACCDATA_EL1, x0
# CHECK-NO-LS64: mrs x0, S3_0_C13_C0_5
# CHECK-NO-LS64: msr S3_0_C13_C0_5, x0