forked from OSchip/llvm-project
[AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension
This adds support for the v8.7-A LD64B/ST64B Accelerator extension through a subtarget feature called "ls64". It adds four 64-byte load/store instructions with an operand in the new GPR64x8 register class, and one system register that's part of the same extension. Based on patches written by Simon Tatham. Reviewed By: ostannard Differential Revision: https://reviews.llvm.org/D91775
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@ -409,6 +409,9 @@ def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
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def FeatureHCX : SubtargetFeature<
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"hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
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def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
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"true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
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def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
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"true", "Enable fine grained virtualization traps extension">;
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@ -11255,6 +11255,35 @@ multiclass STOPregister<string asm, string instr> {
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!cast<Instruction>(instr # "X")>;
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}
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class LoadStore64B_base<bits<3> opc, string asm_inst, string asm_ops,
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dag iops, dag oops, list<dag> pat>
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: I<oops, iops, asm_inst, asm_ops, "", pat>,
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Sched<[]> /* FIXME: fill in scheduling details once known */ {
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bits<5> Rt;
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bits<5> Rn;
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let Inst{31-21} = 0b11111000001;
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let Inst{15} = 1;
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let Inst{14-12} = opc;
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let Inst{11-10} = 0b00;
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let Inst{9-5} = Rn;
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let Inst{4-0} = Rt;
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let Predicates = [HasV8_7a];
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}
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class LoadStore64B<bits<3> opc, string asm_inst, dag iops, dag oops,
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list<dag> pat = []>
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: LoadStore64B_base<opc, asm_inst, "\t$Rt, [$Rn]", iops, oops, pat> {
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let Inst{20-16} = 0b11111;
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}
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class Store64BV<bits<3> opc, string asm_inst, list<dag> pat = []>
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: LoadStore64B_base<opc, asm_inst, "\t$Rs, $Rt, [$Rn]",
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(ins GPR64x8:$Rt, GPR64sp:$Rn), (outs GPR64:$Rs), pat> {
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bits<5> Rs;
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let Inst{20-16} = Rs;
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}
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//----------------------------------------------------------------------------
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// Allow the size specifier tokens to be upper case, not just lower.
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def : TokenAlias<".4B", ".4b">; // Add dot product
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@ -155,6 +155,8 @@ def HasXS : Predicate<"Subtarget->hasXS()">,
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AssemblerPredicate<(all_of FeatureXS), "xs">;
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def HasWFxT : Predicate<"Subtarget->hasWFxT()">,
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AssemblerPredicate<(all_of FeatureWFxT), "wfxt">;
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def HasLS64 : Predicate<"Subtarget->hasLS64()">,
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AssemblerPredicate<(all_of FeatureLS64), "ls64">;
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def IsLE : Predicate<"Subtarget->isLittleEndian()">;
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def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
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def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
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@ -7745,6 +7747,15 @@ let AddedComplexity = 10 in {
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// FIXME: add SVE dot-product patterns.
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}
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let Predicates = [HasLS64] in {
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def LD64B: LoadStore64B<0b101, "ld64b", (ins GPR64sp:$Rn),
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(outs GPR64x8:$Rt)>;
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def ST64B: LoadStore64B<0b001, "st64b", (ins GPR64sp:$Rn, GPR64x8:$Rt),
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(outs)>;
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def ST64BV: Store64BV<0b011, "st64bv">;
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def ST64BV0: Store64BV<0b010, "st64bv0">;
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}
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include "AArch64InstrAtomics.td"
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include "AArch64SVEInstrInfo.td"
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@ -172,6 +172,7 @@ protected:
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bool HasXS = false;
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bool HasWFxT = false;
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bool HasHCX = false;
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bool HasLS64 = false;
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// Arm SVE2 extensions
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bool HasSVE2 = false;
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@ -503,6 +504,7 @@ public:
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bool hasXS() const { return HasXS; }
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bool hasWFxT() const { return HasWFxT; }
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bool hasHCX() const { return HasHCX; }
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bool hasLS64() const { return HasLS64; }
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bool hasSEL2() const { return HasSEL2; }
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bool hasPMU() const { return HasPMU; }
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bool hasTLB_RMI() const { return HasTLB_RMI; }
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@ -1570,6 +1570,10 @@ def : RWSysReg<"CNTPCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b101>;
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def : RWSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>;
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}
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// v8.7a LD64B/ST64B Accelerator Extension system register
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let Requires = [{ {AArch64::FeatureLS64} }] in
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def : RWSysReg<"ACCDATA_EL1", 0b11, 0b000, 0b1101, 0b0000, 0b101>;
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// Cyclone specific system registers
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// Op0 Op1 CRn CRm Op2
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let Requires = [{ {AArch64::ProcAppleA7} }] in
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@ -473,6 +473,7 @@ static const unsigned GPR64x8DecoderTable[] = {
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AArch64::X16_X17_X18_X19_X20_X21_X22_X23,
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AArch64::X18_X19_X20_X21_X22_X23_X24_X25,
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AArch64::X20_X21_X22_X23_X24_X25_X26_X27,
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AArch64::X22_X23_X24_X25_X26_X27_X28_FP,
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};
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static DecodeStatus DecodeGPR64x8ClassRegisterClass(MCInst &Inst,
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@ -0,0 +1,38 @@
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+ls64 < %s 2>%t | FileCheck %s
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// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-LS64-ERR %s < %t
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// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
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// RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-NO-LS64-ERR %s < %t
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ld64b x0, [x13]
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st64b x14, [x13]
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st64bv x1, x20, [x13]
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st64bv0 x1, x22, [x13]
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// CHECK: ld64b x0, [x13] // encoding: [0xa0,0xd1,0x3f,0xf8]
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// CHECK: st64b x14, [x13] // encoding: [0xae,0x91,0x3f,0xf8]
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// CHECK: st64bv x1, x20, [x13] // encoding: [0xb4,0xb1,0x21,0xf8]
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// CHECK: st64bv0 x1, x22, [x13] // encoding: [0xb6,0xa1,0x21,0xf8]
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// CHECK-NO-LS64-ERR: [[@LINE-8]]:3: error: instruction requires: ls64
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// CHECK-NO-LS64-ERR: [[@LINE-8]]:3: error: instruction requires: ls64
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// CHECK-NO-LS64-ERR: [[@LINE-8]]:3: error: instruction requires: ls64
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// CHECK-NO-LS64-ERR: [[@LINE-8]]:3: error: instruction requires: ls64
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ld64b x0, [sp]
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st64b x14, [sp]
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st64bv x1, x20, [sp]
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st64bv0 x1, x22, [sp]
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// CHECK: ld64b x0, [sp] // encoding: [0xe0,0xd3,0x3f,0xf8]
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// CHECK: st64b x14, [sp] // encoding: [0xee,0x93,0x3f,0xf8]
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// CHECK: st64bv x1, x20, [sp] // encoding: [0xf4,0xb3,0x21,0xf8]
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// CHECK: st64bv0 x1, x22, [sp] // encoding: [0xf6,0xa3,0x21,0xf8]
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ld64b x1, [x13]
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ld64b x24, [x13]
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// CHECK-ERR: [[@LINE-2]]:9: error: expected an even-numbered x-register in the range [x0,x22]
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// CHECK-ERR: [[@LINE-2]]:9: error: expected an even-numbered x-register in the range [x0,x22]
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mrs x0, accdata_el1
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msr accdata_el1, x0
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// CHECK: mrs x0, ACCDATA_EL1 // encoding: [0xa0,0xd0,0x38,0xd5]
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// CHECK: msr ACCDATA_EL1, x0 // encoding: [0xa0,0xd0,0x18,0xd5]
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// CHECK-NO-LS64-ERR: [[@LINE-4]]:11: error: expected readable system register
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// CHECK-NO-LS64-ERR: [[@LINE-4]]:7: error: expected writable system register
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@ -0,0 +1,38 @@
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# RUN: not llvm-mc -triple=aarch64 -mattr=+ls64 -disassemble %s 2> %t | FileCheck %s
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# RUN: FileCheck --check-prefix=CHECK-ERR %s < %t
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# RUN: not llvm-mc -triple=aarch64 -disassemble %s 2> %t | FileCheck --check-prefix=CHECK-NO-LS64 %s
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# RUN: FileCheck --check-prefix=CHECK-ERR --check-prefix=CHECK-NO-LS64-ERR %s < %t
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[0xa0,0xd1,0x3f,0xf8]
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[0xae,0x91,0x3f,0xf8]
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[0xb4,0xb1,0x21,0xf8]
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[0xb6,0xa1,0x21,0xf8]
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# CHECK: ld64b x0, [x13]
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# CHECK: st64b x14, [x13]
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# CHECK: st64bv x1, x20, [x13]
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# CHECK: st64bv0 x1, x22, [x13]
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# CHECK-NO-LS64-ERR: [[@LINE-8]]:2: warning: invalid instruction encoding
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# CHECK-NO-LS64-ERR: [[@LINE-8]]:2: warning: invalid instruction encoding
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# CHECK-NO-LS64-ERR: [[@LINE-8]]:2: warning: invalid instruction encoding
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# CHECK-NO-LS64-ERR: [[@LINE-8]]:2: warning: invalid instruction encoding
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[0xe0,0xd3,0x3f,0xf8]
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[0xee,0x93,0x3f,0xf8]
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[0xf4,0xb3,0x21,0xf8]
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[0xf6,0xa3,0x21,0xf8]
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# CHECK: ld64b x0, [sp]
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# CHECK: st64b x14, [sp]
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# CHECK: st64bv x1, x20, [sp]
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# CHECK: st64bv0 x1, x22, [sp]
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[0xb3,0xd1,0x3f,0xf8]
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[0xb8,0xd1,0x3f,0xf8]
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# CHECK-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
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# CHECK-ERR: [[@LINE-2]]:2: warning: invalid instruction encoding
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[0xa0,0xd0,0x38,0xd5]
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[0xa0,0xd0,0x18,0xd5]
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# CHECK: mrs x0, ACCDATA_EL1
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# CHECK: msr ACCDATA_EL1, x0
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# CHECK-NO-LS64: mrs x0, S3_0_C13_C0_5
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# CHECK-NO-LS64: msr S3_0_C13_C0_5, x0
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