forked from OSchip/llvm-project
[X86] Add more ISD nodes to handle masked versions of VCVT(T)PD2DQZ128/VCVT(T)PD2UDQZ128 which only produce 2 result elements and zeroes the upper elements.
We can't represent this properly with vselect like we normally do. We also have to update the instruction definition to use a VK2WM mask instead of VK4WM to represent this. Fixes another case from PR34877 llvm-svn: 351018
This commit is contained in:
Craig Topper
parent
4561edbec0
commit
31156bbdb9
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@ -22059,6 +22059,7 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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return DAG.getMergeValues(Results, dl);
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}
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case CVTPD2PS_MASK:
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case CVTPD2I_MASK:
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case TRUNCATE_TO_REG: {
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SDValue Src = Op.getOperand(1);
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SDValue PassThru = Op.getOperand(2);
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@ -27376,6 +27377,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
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case X86ISD::CVTTP2SI: return "X86ISD::CVTTP2SI";
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case X86ISD::CVTTP2UI: return "X86ISD::CVTTP2UI";
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case X86ISD::MCVTTP2SI: return "X86ISD::MCVTTP2SI";
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case X86ISD::MCVTTP2UI: return "X86ISD::MCVTTP2UI";
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case X86ISD::CVTTP2SI_RND: return "X86ISD::CVTTP2SI_RND";
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case X86ISD::CVTTP2UI_RND: return "X86ISD::CVTTP2UI_RND";
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case X86ISD::CVTTS2SI: return "X86ISD::CVTTS2SI";
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@ -27395,6 +27398,8 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::CVTPH2PS_RND: return "X86ISD::CVTPH2PS_RND";
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case X86ISD::CVTP2SI: return "X86ISD::CVTP2SI";
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case X86ISD::CVTP2UI: return "X86ISD::CVTP2UI";
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case X86ISD::MCVTP2SI: return "X86ISD::MCVTP2SI";
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case X86ISD::MCVTP2UI: return "X86ISD::MCVTP2UI";
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case X86ISD::CVTP2SI_RND: return "X86ISD::CVTP2SI_RND";
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case X86ISD::CVTP2UI_RND: return "X86ISD::CVTP2UI_RND";
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case X86ISD::CVTS2SI: return "X86ISD::CVTS2SI";
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@ -513,6 +513,10 @@ namespace llvm {
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// Vector signed/unsigned integer to float/double.
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CVTSI2P, CVTUI2P,
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// Masked versions of above. Used for v2f64->v4f32.
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// SRC, PASSTHRU, MASK
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MCVTP2SI, MCVTP2UI, MCVTTP2SI, MCVTTP2UI,
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// Save xmm argument registers to the stack, according to %al. An operator
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// is needed so that this can be expanded with control flow.
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VASTART_SAVE_XMM_REGS,
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@ -8214,7 +8214,8 @@ multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
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// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
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// due to the same reason.
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info,
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OpNode, sched.XMM, "{1to2}", "{x}">, EVEX_V128;
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null_frag, sched.XMM, "{1to2}", "{x}", f128mem,
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VK2WM>, EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
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sched.YMM, "{1to4}", "{y}">, EVEX_V256;
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@ -8243,8 +8244,9 @@ multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr, SDNode OpNode,
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// memory forms of these instructions in Asm Parcer. They have the same
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// dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
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// due to the same reason.
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
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sched.XMM, "{1to2}", "{x}">, EVEX_V128;
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info,
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null_frag, sched.XMM, "{1to2}", "{x}", f128mem,
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VK2WM>, EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
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sched.YMM, "{1to4}", "{y}">, EVEX_V256;
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@ -8527,6 +8529,122 @@ let Predicates = [HasVLX] in {
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(VCVTTPD2UDQZ256rr VR256X:$src)>;
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def : Pat<(v4i32 (fp_to_uint (loadv4f64 addr:$src))),
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(VCVTTPD2UDQZ256rm addr:$src)>;
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// Special patterns to allow use of X86mcvtp2Int for masking. Instruction
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// patterns have been disabled with null_frag.
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def : Pat<(v4i32 (X86cvtp2Int (v2f64 VR128X:$src))),
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(VCVTPD2DQZ128rr VR128X:$src)>;
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def : Pat<(X86mcvtp2Int (v2f64 VR128X:$src), (v4i32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTPD2DQZ128rrk VR128X:$src0, VK2WM:$mask, VR128X:$src)>;
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def : Pat<(X86mcvtp2Int (v2f64 VR128X:$src), v4i32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTPD2DQZ128rrkz VK2WM:$mask, VR128X:$src)>;
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def : Pat<(v4i32 (X86cvtp2Int (loadv2f64 addr:$src))),
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(VCVTPD2DQZ128rm addr:$src)>;
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def : Pat<(X86mcvtp2Int (loadv2f64 addr:$src), (v4i32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTPD2DQZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86mcvtp2Int (loadv2f64 addr:$src), v4i32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTPD2DQZ128rmkz VK2WM:$mask, addr:$src)>;
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def : Pat<(v4i32 (X86cvtp2Int (v2f64 (X86VBroadcast (loadf64 addr:$src))))),
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(VCVTPD2DQZ128rmb addr:$src)>;
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def : Pat<(X86mcvtp2Int (v2f64 (X86VBroadcast (loadf64 addr:$src))),
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(v4i32 VR128X:$src0), VK2WM:$mask),
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(VCVTPD2DQZ128rmbk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86mcvtp2Int (v2f64 (X86VBroadcast (loadf64 addr:$src))),
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v4i32x_info.ImmAllZerosV, VK2WM:$mask),
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(VCVTPD2DQZ128rmbkz VK2WM:$mask, addr:$src)>;
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// Special patterns to allow use of X86mcvttp2si for masking. Instruction
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// patterns have been disabled with null_frag.
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def : Pat<(v4i32 (X86cvttp2si (v2f64 VR128X:$src))),
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(VCVTTPD2DQZ128rr VR128X:$src)>;
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def : Pat<(X86mcvttp2si (v2f64 VR128X:$src), (v4i32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTTPD2DQZ128rrk VR128X:$src0, VK2WM:$mask, VR128X:$src)>;
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def : Pat<(X86mcvttp2si (v2f64 VR128X:$src), v4i32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTTPD2DQZ128rrkz VK2WM:$mask, VR128X:$src)>;
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def : Pat<(v4i32 (X86cvttp2si (loadv2f64 addr:$src))),
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(VCVTTPD2DQZ128rm addr:$src)>;
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def : Pat<(X86mcvttp2si (loadv2f64 addr:$src), (v4i32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTTPD2DQZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86mcvttp2si (loadv2f64 addr:$src), v4i32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTTPD2DQZ128rmkz VK2WM:$mask, addr:$src)>;
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def : Pat<(v4i32 (X86cvttp2si (v2f64 (X86VBroadcast (loadf64 addr:$src))))),
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(VCVTTPD2DQZ128rmb addr:$src)>;
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def : Pat<(X86mcvttp2si (v2f64 (X86VBroadcast (loadf64 addr:$src))),
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(v4i32 VR128X:$src0), VK2WM:$mask),
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(VCVTTPD2DQZ128rmbk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86mcvttp2si (v2f64 (X86VBroadcast (loadf64 addr:$src))),
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v4i32x_info.ImmAllZerosV, VK2WM:$mask),
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(VCVTTPD2DQZ128rmbkz VK2WM:$mask, addr:$src)>;
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// Special patterns to allow use of X86mcvtp2UInt for masking. Instruction
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// patterns have been disabled with null_frag.
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def : Pat<(v4i32 (X86cvtp2UInt (v2f64 VR128X:$src))),
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(VCVTPD2UDQZ128rr VR128X:$src)>;
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def : Pat<(X86mcvtp2UInt (v2f64 VR128X:$src), (v4i32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTPD2UDQZ128rrk VR128X:$src0, VK2WM:$mask, VR128X:$src)>;
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def : Pat<(X86mcvtp2UInt (v2f64 VR128X:$src), v4i32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTPD2UDQZ128rrkz VK2WM:$mask, VR128X:$src)>;
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def : Pat<(v4i32 (X86cvtp2UInt (loadv2f64 addr:$src))),
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(VCVTPD2UDQZ128rm addr:$src)>;
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def : Pat<(X86mcvtp2UInt (loadv2f64 addr:$src), (v4i32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTPD2UDQZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86mcvtp2UInt (loadv2f64 addr:$src), v4i32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTPD2UDQZ128rmkz VK2WM:$mask, addr:$src)>;
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def : Pat<(v4i32 (X86cvtp2UInt (v2f64 (X86VBroadcast (loadf64 addr:$src))))),
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(VCVTPD2UDQZ128rmb addr:$src)>;
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def : Pat<(X86mcvtp2UInt (v2f64 (X86VBroadcast (loadf64 addr:$src))),
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(v4i32 VR128X:$src0), VK2WM:$mask),
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(VCVTPD2UDQZ128rmbk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86mcvtp2UInt (v2f64 (X86VBroadcast (loadf64 addr:$src))),
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v4i32x_info.ImmAllZerosV, VK2WM:$mask),
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(VCVTPD2UDQZ128rmbkz VK2WM:$mask, addr:$src)>;
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// Special patterns to allow use of X86mcvtp2UInt for masking. Instruction
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// patterns have been disabled with null_frag.
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def : Pat<(v4i32 (X86cvttp2ui (v2f64 VR128X:$src))),
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(VCVTTPD2UDQZ128rr VR128X:$src)>;
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def : Pat<(X86mcvttp2ui (v2f64 VR128X:$src), (v4i32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTTPD2UDQZ128rrk VR128X:$src0, VK2WM:$mask, VR128X:$src)>;
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def : Pat<(X86mcvttp2ui (v2f64 VR128X:$src), v4i32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTTPD2UDQZ128rrkz VK2WM:$mask, VR128X:$src)>;
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def : Pat<(v4i32 (X86cvttp2ui (loadv2f64 addr:$src))),
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(VCVTTPD2UDQZ128rm addr:$src)>;
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def : Pat<(X86mcvttp2ui (loadv2f64 addr:$src), (v4i32 VR128X:$src0),
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VK2WM:$mask),
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(VCVTTPD2UDQZ128rmk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86mcvttp2ui (loadv2f64 addr:$src), v4i32x_info.ImmAllZerosV,
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VK2WM:$mask),
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(VCVTTPD2UDQZ128rmkz VK2WM:$mask, addr:$src)>;
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def : Pat<(v4i32 (X86cvttp2ui (v2f64 (X86VBroadcast (loadf64 addr:$src))))),
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(VCVTTPD2UDQZ128rmb addr:$src)>;
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def : Pat<(X86mcvttp2ui (v2f64 (X86VBroadcast (loadf64 addr:$src))),
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(v4i32 VR128X:$src0), VK2WM:$mask),
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(VCVTTPD2UDQZ128rmbk VR128X:$src0, VK2WM:$mask, addr:$src)>;
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def : Pat<(X86mcvttp2ui (v2f64 (X86VBroadcast (loadf64 addr:$src))),
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v4i32x_info.ImmAllZerosV, VK2WM:$mask),
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(VCVTTPD2UDQZ128rmbkz VK2WM:$mask, addr:$src)>;
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}
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let Predicates = [HasDQI] in {
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@ -590,6 +590,19 @@ def X86cvtp2Int : SDNode<"X86ISD::CVTP2SI", SDTFloatToInt>;
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def X86cvtp2UInt : SDNode<"X86ISD::CVTP2UI", SDTFloatToInt>;
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def SDTMFloatToInt: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisInt<0>, SDTCisFP<1>,
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SDTCisSameSizeAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<1, 3>]>;
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def X86mcvtp2Int : SDNode<"X86ISD::MCVTP2SI", SDTMFloatToInt>;
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def X86mcvtp2UInt : SDNode<"X86ISD::MCVTP2UI", SDTMFloatToInt>;
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def X86mcvttp2si : SDNode<"X86ISD::MCVTTP2SI", SDTMFloatToInt>;
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def X86mcvttp2ui : SDNode<"X86ISD::MCVTTP2UI", SDTMFloatToInt>;
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def X86cvtph2ps : SDNode<"X86ISD::CVTPH2PS",
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SDTypeProfile<1, 1, [SDTCVecEltisVT<0, f32>,
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SDTCVecEltisVT<1, i16>]> >;
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@ -32,7 +32,7 @@ enum IntrinsicType : uint16_t {
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IFMA_OP, VPERM_2OP, INTR_TYPE_SCALAR_MASK,
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INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK,
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COMPRESS_EXPAND_IN_REG,
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TRUNCATE_TO_REG, CVTPS2PH_MASK,
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TRUNCATE_TO_REG, CVTPS2PH_MASK, CVTPD2I_MASK,
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TRUNCATE_TO_MEM_VI8, TRUNCATE_TO_MEM_VI16, TRUNCATE_TO_MEM_VI32,
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FIXUPIMM, FIXUPIMM_MASKZ, FIXUPIMMS,
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FIXUPIMMS_MASKZ, GATHER_AVX2,
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@ -458,8 +458,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::CONFLICT, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtdq2ps_512, INTR_TYPE_1OP_MASK,
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ISD::SINT_TO_FP, X86ISD::SINT_TO_FP_RND), //er
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_128, CVTPD2I_MASK,
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X86ISD::CVTP2SI, X86ISD::MCVTP2SI),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2dq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2ps, CVTPD2PS_MASK,
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@ -472,8 +472,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::CVTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2qq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2SI, X86ISD::CVTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2udq_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2UI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2udq_128, CVTPD2I_MASK,
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X86ISD::CVTP2UI, X86ISD::MCVTP2UI),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2udq_256, INTR_TYPE_1OP_MASK,
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X86ISD::CVTP2UI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtpd2udq_512, INTR_TYPE_1OP_MASK,
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@ -522,8 +522,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::VFPROUNDS_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvtss2sd_round, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::VFPEXTS_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_128, CVTPD2I_MASK,
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X86ISD::CVTTP2SI, X86ISD::MCVTTP2SI),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2dq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTTP2SI, X86ISD::CVTTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2qq_128, INTR_TYPE_1OP_MASK,
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@ -532,8 +532,8 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::CVTTP2SI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2qq_512, INTR_TYPE_1OP_MASK,
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X86ISD::CVTTP2SI, X86ISD::CVTTP2SI_RND),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_128, INTR_TYPE_1OP_MASK,
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X86ISD::CVTTP2UI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_128, CVTPD2I_MASK,
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X86ISD::CVTTP2UI, X86ISD::MCVTTP2UI),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_256, INTR_TYPE_1OP_MASK,
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X86ISD::CVTTP2UI, 0),
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X86_INTRINSIC_DATA(avx512_mask_cvttpd2udq_512, INTR_TYPE_1OP_MASK,
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