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[Mips Assembler] Add support for OR macro with imediate opperand 

Mips assembler supports macros that allows the OR instruction 
to have an immediate parameter. This patch adds an instruction 
alias that converts this macro into a Mips ORI instruction. 

Contributer: Vladimir Medic
llvm-svn: 178316
This commit is contained in:
Jack Carter 2013-03-28 23:45:13 +00:00
parent 3faf47c462
commit 311246c6d5
3 changed files with 8 additions and 1 deletions
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4
llvm/lib/Target/Mips/Mips64InstrInfo.td
View File

@ -342,7 +342,9 @@ def : InstAlias<"daddu $rs, $rt, $imm",
def : InstAlias<"dadd $rs, $rt, $imm", def : InstAlias<"dadd $rs, $rt, $imm",
(DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm), (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
1>; 1>;
def : InstAlias<"or $rs, $rt, $imm",
(ORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
1>, Requires<[HasMips64]>;
/// Move between CPU and coprocessor registers /// Move between CPU and coprocessor registers
let DecoderNamespace = "Mips64" in { let DecoderNamespace = "Mips64" in {

3
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -1015,6 +1015,9 @@ def : InstAlias<"slt $rs, $rt, $imm",
def : InstAlias<"xor $rs, $rt, $imm", def : InstAlias<"xor $rs, $rt, $imm",
(XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>,
Requires<[NotMips64]>; Requires<[NotMips64]>;
def : InstAlias<"or $rs, $rt, $imm",
(ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>,
Requires<[NotMips64]>;
def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
def : InstAlias<"mfc0 $rt, $rd", def : InstAlias<"mfc0 $rt, $rd",
(MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;

2
llvm/test/MC/Mips/mips-alu-instructions.s
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@ -13,6 +13,7 @@
# CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d] # CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
# CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00] # CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
# CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00] # CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34]
# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34] # CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
# CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00] # CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
# CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00] # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
@ -40,6 +41,7 @@
ins $19, $9, 6,7 ins $19, $9, 6,7
nor $9, $6, $7 nor $9, $6, $7
or $3, $3, $5 or $3, $3, $5
or $4, $5, 17767
ori $9, $6, 17767 ori $9, $6, 17767
rotr $9, $6, 7 rotr $9, $6, 7
rotrv $9, $6, $7 rotrv $9, $6, $7