forked from OSchip/llvm-project
[ARM] Guard the declarations of f16 to f32 vcvt intrinsics in arm_neon.h by testing __ARM_FP
Summary: Conversions between float and half are only available when the taraget has the half-precision extension. Guard these intrinsics so that they don't cause crashes in the backend. Fixes PR27550. Reviewers: rengolin, t.p.northover Subscribers: cfe-commits, aemerson, t.p.northover, rengolin Differential Revision: http://reviews.llvm.org/D19665 llvm-svn: 268047
This commit is contained in:
parent
14824b1c52
commit
3102a01258
|
@ -704,8 +704,10 @@ def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
|
|||
////////////////////////////////////////////////////////////////////////////////
|
||||
// E.3.22 Converting vectors
|
||||
|
||||
def VCVT_F16_F32 : SInst<"vcvt_f16_f32", "md", "Hf">;
|
||||
def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "wd", "h">;
|
||||
let ArchGuard = "(__ARM_FP & 2)" in {
|
||||
def VCVT_F16_F32 : SInst<"vcvt_f16_f32", "md", "Hf">;
|
||||
def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "wd", "h">;
|
||||
}
|
||||
|
||||
def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">;
|
||||
def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">;
|
||||
|
|
|
@ -0,0 +1,11 @@
|
|||
// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon -target-feature -fp16 -fsyntax-only -verify
|
||||
|
||||
#include <arm_neon.h>
|
||||
|
||||
float16x4_t test_vcvt_f16_f32(float32x4_t a) {
|
||||
return vcvt_f16_f32(a); // expected-warning{{implicit declaration of function 'vcvt_f16_f32'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
|
||||
}
|
||||
|
||||
float32x4_t test_vcvt_f32_f16(float16x4_t a) {
|
||||
return vcvt_f32_f16(a); // expected-warning{{implicit declaration of function 'vcvt_f32_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float32x4_t'}}
|
||||
}
|
Loading…
Reference in New Issue