diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 37f269ccb607..c263ac4ac848 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1905,7 +1905,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { .addImm(AMDGPU::VGPRIndexMode::DST_ENABLE); SetOn->getOperand(3).setIsUndef(); - const MCInstrDesc &OpDesc = get(AMDGPU::V_MOV_B32_indirect); + const MCInstrDesc &OpDesc = get(AMDGPU::V_MOV_B32_indirect_write); MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, OpDesc) .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) @@ -1945,7 +1945,7 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { .addImm(AMDGPU::VGPRIndexMode::SRC0_ENABLE); SetOn->getOperand(3).setIsUndef(); - BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32)) + BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_indirect_read)) .addDef(Dst) .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) .addReg(VecReg, RegState::Implicit | (IsUndef ? RegState::Undef : 0)) @@ -2716,14 +2716,7 @@ bool SIInstrInfo::isFoldableCopy(const MachineInstr &MI) { switch (MI.getOpcode()) { case AMDGPU::V_MOV_B32_e32: case AMDGPU::V_MOV_B32_e64: - case AMDGPU::V_MOV_B64_PSEUDO: { - // If there are additional implicit register operands, this may be used for - // register indexing so the source register operand isn't simply copied. - unsigned NumOps = MI.getDesc().getNumOperands() + - MI.getDesc().getNumImplicitUses(); - - return MI.getNumOperands() == NumOps; - } + case AMDGPU::V_MOV_B64_PSEUDO: case AMDGPU::S_MOV_B32: case AMDGPU::S_MOV_B64: case AMDGPU::COPY: diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp index ee155d4b202d..d1b8e217471e 100644 --- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp +++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp @@ -257,10 +257,8 @@ bool SIPreEmitPeephole::optimizeSetGPR(MachineInstr &First, })) { // The only exception allowed here is another indirect vector move // with the same mode. - if (!IdxOn || - !((I->getOpcode() == AMDGPU::V_MOV_B32_e32 && - I->hasRegisterImplicitUseOperand(AMDGPU::M0)) || - I->getOpcode() == AMDGPU::V_MOV_B32_indirect)) + if (!IdxOn || !(I->getOpcode() == AMDGPU::V_MOV_B32_indirect_write || + I->getOpcode() == AMDGPU::V_MOV_B32_indirect_read)) return false; } } diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td index 35d5fe13ad30..9c398e3a132a 100644 --- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td @@ -863,7 +863,7 @@ defm V_ACCVGPR_MOV_B32 : VOP1Only_Real_vi<0x52>; // Copy of v_mov_b32 with $vdst as a use operand for use with VGPR // indexing mode. vdst can't be treated as a def for codegen purposes, // and an implicit use and def of the super register should be added. -def V_MOV_B32_indirect : VPseudoInstSI<(outs), +def V_MOV_B32_indirect_write : VPseudoInstSI<(outs), (ins getVALUDstForVT.ret:$vdst, getVOPSrc0ForVT.ret:$src0)>, PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT.ret:$vdst, getVOPSrc0ForVT.ret:$src0)> { @@ -871,6 +871,17 @@ def V_MOV_B32_indirect : VPseudoInstSI<(outs), let SubtargetPredicate = isGFX8GFX9; } +// Copy of v_mov_b32 for use with VGPR indexing mode. An implicit use of the +// super register should be added. +def V_MOV_B32_indirect_read : VPseudoInstSI< + (outs getVALUDstForVT.ret:$vdst), + (ins getVOPSrc0ForVT.ret:$src0)>, + PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT.ret:$vdst, + getVOPSrc0ForVT.ret:$src0)> { + let VOP1 = 1; + let SubtargetPredicate = isGFX8GFX9; +} + let OtherPredicates = [isGFX8Plus] in { def : GCNPat < diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll index c94812199bd9..8eed661d0d05 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -9251,37 +9251,38 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: s_movk_i32 s4, 0xfee0 ; GFX6-NEXT: s_mov_b32 s5, 0x68958c89 -; GFX6-NEXT: v_mov_b32_e32 v8, 0 +; GFX6-NEXT: v_mov_b32_e32 v7, 0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX6-NEXT: v_mov_b32_e32 v7, 0 ; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GFX6-NEXT: s_movk_i32 s8, 0x11f ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s5 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s5 -; GFX6-NEXT: s_movk_i32 s8, 0x11f ; GFX6-NEXT: s_mov_b32 s9, 0x976a7377 +; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s5 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 -; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v6, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3 +; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GFX6-NEXT: s_mov_b32 s6, -1 +; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4 @@ -9289,26 +9290,24 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s5 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_mov_b32 s4, s0 -; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s5 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 ; GFX6-NEXT: s_mov_b32 s5, s1 -; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1 @@ -9317,14 +9316,14 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s8 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s9 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s9 @@ -9374,96 +9373,95 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: s_movk_i32 s2, 0xfee0 ; GFX9-NEXT: s_mov_b32 s3, 0x68958c89 -; GFX9-NEXT: v_mov_b32_e32 v8, 0 +; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3 -; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3 -; GFX9-NEXT: v_mul_lo_u32 v6, v0, s3 +; GFX9-NEXT: v_mul_lo_u32 v5, v1, s3 +; GFX9-NEXT: v_mul_lo_u32 v4, v0, s3 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 -; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 +; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4 +; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc -; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6 -; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc +; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 +; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3 -; GFX9-NEXT: v_mul_lo_u32 v6, v0, s3 +; GFX9-NEXT: v_mul_lo_u32 v5, v0, s3 ; GFX9-NEXT: s_movk_i32 s2, 0x11f ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6 +; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc -; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6 -; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v7, vcc +; GFX9-NEXT: v_mul_lo_u32 v7, v1, v5 +; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: s_mov_b32 s3, 0x976a7377 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 -; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 +; GFX9-NEXT: v_mul_hi_u32 v5, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v6, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3 -; GFX9-NEXT: v_mov_b32_e32 v6, s2 +; GFX9-NEXT: v_mov_b32_e32 v5, s2 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s3 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_sub_u32_e32 v4, s7, v2 ; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s6, v3 -; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v6, vcc -; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s3, v3 +; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v5, vcc +; GFX9-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s3, v3 ; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1] ; GFX9-NEXT: s_movk_i32 s3, 0x11e ; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s3, v4 ; GFX9-NEXT: s_mov_b32 s6, 0x976a7376 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] -; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s6, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GFX9-NEXT: v_cmp_lt_u32_e64 s[0:1], s6, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s2, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v6, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v5, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v7, s7 ; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v7, v2, vcc ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s3, v2 @@ -9475,11 +9473,11 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s2, v2 ; GFX9-NEXT: v_add_co_u32_e64 v4, s[0:1], v0, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v2, v7, v3, vcc -; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], 0, v1, s[0:1] +; GFX9-NEXT: v_addc_co_u32_e64 v5, s[0:1], 0, v1, s[0:1] ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc -; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5] +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5] ; GFX9-NEXT: s_endpgm ; ; GFX90A-LABEL: udiv_i64_oddk_denom: @@ -9497,8 +9495,8 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX90A-NEXT: v_mov_b32_e32 v8, 0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 +; GFX90A-NEXT: s_mov_b32 s3, 0x976a7377 ; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s2 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s0 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 @@ -9509,16 +9507,16 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc -; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v4, v0, s2 @@ -9531,16 +9529,16 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc -; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) @@ -9548,7 +9546,7 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0 ; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 @@ -9558,8 +9556,7 @@ define amdgpu_kernel void @udiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX90A-NEXT: s_movk_i32 s2, 0x11f -; GFX90A-NEXT: s_mov_b32 s3, 0x976a7377 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s2 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s3 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 @@ -9778,61 +9775,60 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: s_movk_i32 s6, 0xf001 -; GFX6-NEXT: v_mov_b32_e32 v8, 0 ; GFX6-NEXT: v_mov_b32_e32 v7, 0 +; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 -; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0xd -; GFX6-NEXT: s_mov_b32 s7, 0xf000 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: s_lshr_b64 s[8:9], s[0:1], 12 +; GFX6-NEXT: s_movk_i32 s0, 0xfff ; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, s6 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s6 -; GFX6-NEXT: s_waitcnt lgkmcnt(0) -; GFX6-NEXT: s_lshr_b64 s[8:9], s[0:1], 12 +; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4 -; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v5, v0, v4 +; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, s6 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s6 -; GFX6-NEXT: s_movk_i32 s0, 0xfff +; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, v4 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 -; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1 @@ -9841,14 +9837,14 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s0 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0 @@ -9888,36 +9884,35 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x457ff000 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: s_movk_i32 s2, 0xf001 -; GFX9-NEXT: v_mov_b32_e32 v7, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 ; GFX9-NEXT: s_movk_i32 s8, 0xfff +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, s2 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s2 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, s2 -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v3 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 -; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc -; GFX9-NEXT: v_mul_lo_u32 v8, v1, v3 +; GFX9-NEXT: v_mul_lo_u32 v7, v1, v3 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8 +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc +; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 +; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_mul_hi_u32 v2, v0, s2 @@ -9929,19 +9924,19 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX9-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v6, v0, v4 -; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 +; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v6, v3 -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc -; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc +; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: s_movk_i32 s4, 0xffe -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 @@ -9950,14 +9945,14 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8 @@ -9994,7 +9989,6 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GFX90A-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x34 -; GFX90A-NEXT: v_mov_b32_e32 v8, 0 ; GFX90A-NEXT: v_mov_b32_e32 v4, 0 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 @@ -10014,16 +10008,16 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, v2 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc -; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc +; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v9, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s4 @@ -10035,23 +10029,23 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, v2 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc -; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc +; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v9, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0 ; GFX90A-NEXT: v_mul_hi_u32 v2, s6, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v8, v2, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 @@ -10060,7 +10054,7 @@ define amdgpu_kernel void @udiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v2, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc ; GFX90A-NEXT: s_movk_i32 s4, 0xfff ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, s4 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s4 @@ -10184,64 +10178,64 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: s_movk_i32 s2, 0xfee0 ; GFX6-NEXT: s_mov_b32 s3, 0x689e0837 -; GFX6-NEXT: v_mov_b32_e32 v8, 0 +; GFX6-NEXT: v_mov_b32_e32 v7, 0 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX6-NEXT: v_mov_b32_e32 v7, 0 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX6-NEXT: s_mov_b32 s12, 0x9761f7c9 ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3 -; GFX6-NEXT: s_mov_b32 s12, 0x9761f7c9 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_mov_b32 s8, s4 +; GFX6-NEXT: s_movk_i32 s4, 0x11f ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 -; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v6, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v4, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3 +; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v3, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GFX6-NEXT: s_mov_b32 s9, s5 +; GFX6-NEXT: s_movk_i32 s5, 0x11e +; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s3 -; GFX6-NEXT: s_movk_i32 s4, 0x11f -; GFX6-NEXT: s_mov_b32 s9, s5 +; GFX6-NEXT: s_mov_b32 s11, 0xf000 +; GFX6-NEXT: s_mov_b32 s10, -1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, v3 ; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3 -; GFX6-NEXT: s_movk_i32 s5, 0x11e -; GFX6-NEXT: s_mov_b32 s11, 0xf000 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s6, v1 @@ -10250,15 +10244,14 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX6-NEXT: v_mul_hi_u32 v5, s7, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0 -; GFX6-NEXT: s_mov_b32 s10, -1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v0, s4 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s12 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s12 @@ -10306,77 +10299,76 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: s_movk_i32 s2, 0xfee0 ; GFX9-NEXT: s_mov_b32 s3, 0x689e0837 -; GFX9-NEXT: v_mov_b32_e32 v8, 0 +; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX9-NEXT: v_mov_b32_e32 v5, 0 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NEXT: s_movk_i32 s8, 0x11f ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3 -; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3 -; GFX9-NEXT: v_mul_lo_u32 v6, v0, s3 -; GFX9-NEXT: s_movk_i32 s8, 0x11f -; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 -; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 -; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6 -; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 -; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc -; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6 -; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6 +; GFX9-NEXT: v_mul_lo_u32 v5, v1, s3 +; GFX9-NEXT: v_mul_lo_u32 v4, v0, s3 ; GFX9-NEXT: s_mov_b32 s9, 0x9761f7c9 +; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v5 +; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4 +; GFX9-NEXT: v_mul_lo_u32 v5, v0, v2 +; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 +; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 +; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc +; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 +; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: s_mov_b32 s10, 0x9761f7c8 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s2 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, s3 -; GFX9-NEXT: v_mul_lo_u32 v6, v0, s3 +; GFX9-NEXT: v_mul_lo_u32 v5, v0, s3 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 ; GFX9-NEXT: v_mul_lo_u32 v3, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v4, v0, v6 +; GFX9-NEXT: v_mul_hi_u32 v4, v0, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v7, vcc -; GFX9-NEXT: v_mul_lo_u32 v7, v1, v6 -; GFX9-NEXT: v_mul_hi_u32 v6, v1, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v7, vcc +; GFX9-NEXT: v_mul_lo_u32 v7, v1, v5 +; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v6, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v4, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v1 -; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 +; GFX9-NEXT: v_mul_hi_u32 v5, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_mul_lo_u32 v4, s7, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v6, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v0, s8 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s9 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s9 @@ -10388,14 +10380,14 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s6, v0 ; GFX9-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, vcc ; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[0:1], s9, v0 -; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[2:3], 0, v2, s[0:1] +; GFX9-NEXT: v_subbrev_co_u32_e64 v5, s[2:3], 0, v2, s[0:1] ; GFX9-NEXT: s_movk_i32 s6, 0x11e -; GFX9-NEXT: v_cmp_lt_u32_e64 s[2:3], s6, v6 +; GFX9-NEXT: v_cmp_lt_u32_e64 s[2:3], s6, v5 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] ; GFX9-NEXT: v_cmp_lt_u32_e64 s[2:3], s10, v4 ; GFX9-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3] -; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s8, v6 +; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s8, v5 ; GFX9-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s9, v4 ; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3] ; GFX9-NEXT: v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1] @@ -10406,14 +10398,14 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s6, v1 ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s10, v0 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s8, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX9-NEXT: global_store_dwordx2 v5, v[0:1], s[4:5] +; GFX9-NEXT: global_store_dwordx2 v6, v[0:1], s[4:5] ; GFX9-NEXT: s_endpgm ; ; GFX90A-LABEL: urem_i64_oddk_denom: @@ -10431,8 +10423,8 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX90A-NEXT: v_mov_b32_e32 v8, 0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 +; GFX90A-NEXT: s_movk_i32 s8, 0x11f ; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s2 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s0 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 @@ -10443,16 +10435,16 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc -; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v4, v0, s2 @@ -10465,16 +10457,16 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc -; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) @@ -10482,7 +10474,7 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v0 ; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 @@ -10491,9 +10483,8 @@ define amdgpu_kernel void @urem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX90A-NEXT: s_movk_i32 s8, 0x11f ; GFX90A-NEXT: s_mov_b32 s9, 0x9761f7c9 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v0, s8 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s9 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 @@ -10807,62 +10798,64 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: s_mov_b32 s5, 0xffed2705 -; GFX6-NEXT: v_mov_b32_e32 v8, 0 ; GFX6-NEXT: v_mov_b32_e32 v7, 0 +; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GFX6-NEXT: s_mov_b32 s7, 0xf000 -; GFX6-NEXT: v_mul_lo_u32 v2, v1, s5 -; GFX6-NEXT: v_mul_hi_u32 v3, v0, s5 -; GFX6-NEXT: v_mul_lo_u32 v4, v0, s5 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_ashr_i32 s8, s3, 31 ; GFX6-NEXT: s_add_u32 s2, s2, s8 +; GFX6-NEXT: v_mul_lo_u32 v2, v1, s5 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, s5 +; GFX6-NEXT: v_mul_lo_u32 v4, v0, s5 +; GFX6-NEXT: s_mov_b32 s9, s8 +; GFX6-NEXT: s_addc_u32 s3, s3, s8 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 -; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4 -; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX6-NEXT: v_mul_lo_u32 v3, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v5, v0, v4 +; GFX6-NEXT: v_mul_hi_u32 v6, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9] +; GFX6-NEXT: s_mov_b32 s4, s0 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s5 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s5 -; GFX6-NEXT: s_mov_b32 s9, s8 -; GFX6-NEXT: s_addc_u32 s3, s3, s8 -; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9] +; GFX6-NEXT: s_mov_b32 s0, 0x12d8fb +; GFX6-NEXT: s_mov_b32 s7, 0xf000 +; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s5 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 ; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v10, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v0, v3 +; GFX6-NEXT: v_mul_hi_u32 v9, v0, v2 ; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc +; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6 +; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v9, v5, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1 @@ -10871,16 +10864,15 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0 -; GFX6-NEXT: s_mov_b32 s4, s0 -; GFX6-NEXT: s_mov_b32 s0, 0x12d8fb +; GFX6-NEXT: s_mov_b32 s5, s1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s0 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0 @@ -10898,7 +10890,6 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX6-NEXT: v_cmp_lt_u32_e32 vcc, s0, v5 ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9 -; GFX6-NEXT: s_mov_b32 s5, s1 ; GFX6-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc ; GFX6-NEXT: v_cmp_lt_u32_e64 s[0:1], s0, v8 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 @@ -10914,7 +10905,6 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX6-NEXT: v_xor_b32_e32 v1, s8, v1 ; GFX6-NEXT: v_mov_b32_e32 v2, s8 ; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0 -; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX6-NEXT: s_endpgm @@ -10925,15 +10915,14 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: s_mov_b32 s4, 0xffed2705 -; GFX9-NEXT: v_mov_b32_e32 v7, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4 @@ -10942,17 +10931,17 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 -; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc -; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 +; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc +; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 +; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4 @@ -10963,20 +10952,20 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: s_add_u32 s2, s2, s4 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 -; GFX9-NEXT: v_mul_lo_u32 v8, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v0, v4 -; GFX9-NEXT: v_mul_hi_u32 v10, v0, v2 +; GFX9-NEXT: v_mul_lo_u32 v7, v0, v2 +; GFX9-NEXT: v_mul_hi_u32 v8, v0, v4 +; GFX9-NEXT: v_mul_hi_u32 v9, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v7, v10, vcc +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v6, vcc +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_addc_u32 s3, s3, s4 @@ -10988,7 +10977,7 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_mul_hi_u32 v6, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX9-NEXT: s_mov_b32 s5, 0x12d8fb @@ -10996,7 +10985,7 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s5 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s5 @@ -11036,15 +11025,14 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: s_mov_b32 s4, 0xffed2705 -; GFX90A-NEXT: v_mov_b32_e32 v8, 0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 +; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX90A-NEXT: v_trunc_f32_e32 v1, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s4 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s4 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 @@ -11054,16 +11042,16 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc -; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s4 @@ -11073,20 +11061,20 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, s4 ; GFX90A-NEXT: v_mul_hi_u32 v6, v1, v5 ; GFX90A-NEXT: v_mul_lo_u32 v7, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v3 +; GFX90A-NEXT: v_mul_lo_u32 v9, v0, v3 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5 -; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v3 -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10 -; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, v8, v9, vcc +; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v3 +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9 +; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v8, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX90A-NEXT: v_mul_hi_u32 v4, v1, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v6, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_ashr_i32 s4, s3, 31 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX90A-NEXT: s_add_u32 s2, s2, s4 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: s_mov_b32 s5, s4 @@ -11097,7 +11085,7 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_hi_u32 v5, s2, v0 ; GFX90A-NEXT: v_mul_hi_u32 v3, s2, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: v_mul_hi_u32 v6, s3, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s3, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 @@ -11106,7 +11094,7 @@ define amdgpu_kernel void @sdiv_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX90A-NEXT: s_mov_b32 s5, 0x12d8fb ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s5 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s5 @@ -11260,9 +11248,8 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc ; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc -; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1 @@ -11272,26 +11259,26 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v3, s4, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 -; GFX6-NEXT: v_mul_lo_u32 v8, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v10, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3 +; GFX6-NEXT: v_mul_lo_u32 v7, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v0, v3 +; GFX6-NEXT: v_mul_hi_u32 v9, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v5, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v8, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v9, v7, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v7, v3 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0 ; GFX6-NEXT: v_mul_hi_u32 v5, s2, v1 -; GFX6-NEXT: v_mul_hi_u32 v7, s3, v1 +; GFX6-NEXT: v_mul_hi_u32 v6, s3, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc @@ -11300,9 +11287,9 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX6-NEXT: s_mov_b32 s4, s0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1 ; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0 ; GFX6-NEXT: v_mul_lo_u32 v4, s11, v0 @@ -11390,34 +11377,33 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc -; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX9-NEXT: v_mul_lo_u32 v3, s10, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s10, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s4, v0 -; GFX9-NEXT: v_mul_lo_u32 v7, s10, v0 +; GFX9-NEXT: v_mul_lo_u32 v6, s10, v0 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 -; GFX9-NEXT: v_mul_lo_u32 v8, v0, v3 -; GFX9-NEXT: v_mul_hi_u32 v9, v0, v7 -; GFX9-NEXT: v_mul_hi_u32 v10, v0, v3 -; GFX9-NEXT: v_mul_hi_u32 v5, v1, v7 -; GFX9-NEXT: v_mul_lo_u32 v7, v1, v7 +; GFX9-NEXT: v_mul_lo_u32 v7, v0, v3 +; GFX9-NEXT: v_mul_hi_u32 v8, v0, v6 +; GFX9-NEXT: v_mul_hi_u32 v9, v0, v3 +; GFX9-NEXT: v_mul_hi_u32 v5, v1, v6 +; GFX9-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v3 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc -; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc +; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3 +; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_ashr_i32 s10, s7, 31 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX9-NEXT: s_add_u32 s0, s6, s10 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: s_mov_b32 s11, s10 @@ -11427,7 +11413,7 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX9-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 -; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 +; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc @@ -11435,9 +11421,9 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v2, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX9-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s8, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s9, v0 @@ -11526,9 +11512,8 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 -; GFX90A-NEXT: v_mov_b32_e32 v6, 0 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, s0, v1 @@ -11537,20 +11522,20 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX90A-NEXT: v_mul_lo_u32 v4, s1, v0 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v0 -; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v3 +; GFX90A-NEXT: v_mul_hi_u32 v6, v1, v5 +; GFX90A-NEXT: v_mul_lo_u32 v7, v1, v5 +; GFX90A-NEXT: v_mul_lo_u32 v9, v0, v3 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5 -; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v3 -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10 -; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8 +; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v3 +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9 +; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v8, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX90A-NEXT: v_mul_hi_u32 v4, v1, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX90A-NEXT: s_add_u32 s0, s6, s10 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: s_addc_u32 s1, s7, s10 @@ -11561,15 +11546,15 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc -; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v0 +; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s7, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, s8, v1 ; GFX90A-NEXT: v_mul_hi_u32 v4, s8, v0 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 @@ -11755,9 +11740,8 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc ; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc -; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s6 @@ -11768,26 +11752,26 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s6 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 -; GFX6-NEXT: v_mul_lo_u32 v8, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v10, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3 +; GFX6-NEXT: v_mul_lo_u32 v7, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v0, v3 +; GFX6-NEXT: v_mul_hi_u32 v9, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v5, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v8, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v9, v7, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v7, v3 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1 ; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0 ; GFX6-NEXT: v_mul_hi_u32 v5, s0, v1 -; GFX6-NEXT: v_mul_hi_u32 v7, s1, v1 +; GFX6-NEXT: v_mul_hi_u32 v6, s1, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s1, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc @@ -11797,9 +11781,9 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GFX6-NEXT: v_mul_lo_u32 v4, v1, s2 ; GFX6-NEXT: v_mul_hi_u32 v5, v0, s2 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 2, v0 @@ -11877,9 +11861,8 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc -; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8 @@ -11889,20 +11872,20 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 -; GFX9-NEXT: v_mul_lo_u32 v8, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v0, v5 -; GFX9-NEXT: v_mul_hi_u32 v10, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v7, v1, v5 +; GFX9-NEXT: v_mul_lo_u32 v7, v0, v2 +; GFX9-NEXT: v_mul_hi_u32 v8, v0, v5 +; GFX9-NEXT: v_mul_hi_u32 v9, v0, v2 +; GFX9-NEXT: v_mul_hi_u32 v6, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v8, v5 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: s_addc_u32 s7, s7, s4 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc @@ -11910,7 +11893,7 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX9-NEXT: v_mul_lo_u32 v2, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 -; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 +; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc @@ -11920,9 +11903,9 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v7, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s5 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, s5 @@ -11996,9 +11979,8 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX90A-NEXT: v_mov_b32_e32 v6, 0 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, s4 @@ -12006,23 +11988,23 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX90A-NEXT: v_sub_u32_e32 v2, v2, v0 ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, s4 -; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v2 +; GFX90A-NEXT: v_mul_hi_u32 v6, v1, v5 +; GFX90A-NEXT: v_mul_lo_u32 v7, v1, v5 +; GFX90A-NEXT: v_mul_lo_u32 v9, v0, v2 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5 -; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v2 -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10 -; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8 +; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v2 +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9 +; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v8, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX90A-NEXT: v_mul_hi_u32 v3, v1, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc ; GFX90A-NEXT: s_addc_u32 s1, s5, 0 ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX90A-NEXT: s_ashr_i64 s[0:1], s[0:1], 12 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2 ; GFX90A-NEXT: s_ashr_i32 s4, s7, 31 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: s_add_u32 s6, s6, s4 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX90A-NEXT: s_mov_b32 s5, s4 @@ -12034,15 +12016,15 @@ define amdgpu_kernel void @ssdiv_v2i64_mixed_pow2k_denom(<2 x i64> addrspace(1)* ; GFX90A-NEXT: v_mul_hi_u32 v2, s6, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc -; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v0 +; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s7, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc ; GFX90A-NEXT: s_movk_i32 s5, 0xfff ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, s5 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s5 @@ -12125,209 +12107,208 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1 -; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1 -; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v0 +; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v0 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_ashr_i32 s14, s1, 31 ; GFX6-NEXT: s_add_u32 s0, s0, s14 -; GFX6-NEXT: v_mul_lo_u32 v0, s6, v2 -; GFX6-NEXT: v_mul_hi_u32 v1, s6, v3 -; GFX6-NEXT: v_mul_lo_u32 v4, s7, v3 -; GFX6-NEXT: v_mul_lo_u32 v5, s6, v3 +; GFX6-NEXT: v_mul_lo_u32 v0, s6, v1 +; GFX6-NEXT: v_mul_hi_u32 v3, s6, v2 +; GFX6-NEXT: v_mul_lo_u32 v4, s7, v2 +; GFX6-NEXT: v_mul_lo_u32 v5, s6, v2 ; GFX6-NEXT: s_mov_b32 s15, s14 -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 -; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v4 -; GFX6-NEXT: v_mul_lo_u32 v0, v3, v1 -; GFX6-NEXT: v_mul_hi_u32 v4, v3, v5 -; GFX6-NEXT: v_mul_hi_u32 v6, v3, v1 -; GFX6-NEXT: v_mul_hi_u32 v7, v2, v1 -; GFX6-NEXT: s_addc_u32 s1, s1, s14 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v0, v4 +; GFX6-NEXT: v_mul_lo_u32 v0, v2, v3 +; GFX6-NEXT: v_mul_hi_u32 v4, v2, v5 +; GFX6-NEXT: v_mul_hi_u32 v6, v2, v3 +; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3 +; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0 ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc -; GFX6-NEXT: v_mul_lo_u32 v6, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5 +; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5 +; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5 +; GFX6-NEXT: s_addc_u32 s1, s1, s14 ; GFX6-NEXT: s_xor_b64 s[16:17], s[0:1], s[14:15] -; GFX6-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13] ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc -; GFX6-NEXT: v_mul_lo_u32 v5, v2, v1 ; GFX6-NEXT: v_mov_b32_e32 v0, 0 -; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v7, v0, vcc -; GFX6-NEXT: v_mov_b32_e32 v1, 0 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v6, vcc -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s6, v2 -; GFX6-NEXT: v_mul_hi_u32 v5, s6, v3 -; GFX6-NEXT: v_mul_lo_u32 v6, s7, v3 +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc +; GFX6-NEXT: v_mul_lo_u32 v3, s6, v1 +; GFX6-NEXT: v_mul_hi_u32 v4, s6, v2 +; GFX6-NEXT: v_mul_lo_u32 v5, s7, v2 +; GFX6-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13] ; GFX6-NEXT: s_ashr_i32 s12, s9, 31 -; GFX6-NEXT: s_add_u32 s8, s8, s12 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_mul_lo_u32 v5, s6, v3 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v6, v4 -; GFX6-NEXT: v_mul_lo_u32 v8, v3, v4 -; GFX6-NEXT: v_mul_hi_u32 v9, v3, v5 -; GFX6-NEXT: v_mul_hi_u32 v10, v3, v4 -; GFX6-NEXT: v_mul_hi_u32 v7, v2, v5 -; GFX6-NEXT: v_mul_lo_u32 v5, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v6, v2, v4 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, v2, v4 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v6, v0, vcc -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v6, vcc -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s16, v2 -; GFX6-NEXT: v_mul_hi_u32 v5, s16, v3 -; GFX6-NEXT: v_mul_hi_u32 v6, s16, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, s17, v2 -; GFX6-NEXT: v_mul_lo_u32 v2, s17, v2 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc -; GFX6-NEXT: v_mul_lo_u32 v6, s17, v3 -; GFX6-NEXT: v_mul_hi_u32 v3, s17, v3 -; GFX6-NEXT: s_mov_b32 s13, s12 -; GFX6-NEXT: s_addc_u32 s9, s9, s12 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v0, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v4, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s10, v3 -; GFX6-NEXT: v_mul_hi_u32 v5, s10, v2 -; GFX6-NEXT: v_mul_lo_u32 v6, s11, v2 -; GFX6-NEXT: v_mov_b32_e32 v7, s11 -; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13] -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_mul_lo_u32 v5, s10, v2 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s17, v4 -; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s16, v5 -; GFX6-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc -; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s10, v5 -; GFX6-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7 -; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] -; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1] -; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v2 -; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1] -; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v2 -; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1] -; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1] -; GFX6-NEXT: v_mov_b32_e32 v8, s17 -; GFX6-NEXT: v_cvt_f32_u32_e32 v10, s8 -; GFX6-NEXT: v_cvt_f32_u32_e32 v11, s9 -; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v8, v4, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v5 -; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s11, v4 -; GFX6-NEXT: v_mac_f32_e32 v10, s18, v11 -; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v5, vcc -; GFX6-NEXT: v_rcp_f32_e32 v5, v10 -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc -; GFX6-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1] -; GFX6-NEXT: v_mul_f32_e32 v5, s19, v5 -; GFX6-NEXT: v_mul_f32_e32 v6, s20, v5 -; GFX6-NEXT: v_trunc_f32_e32 v6, v6 -; GFX6-NEXT: v_mac_f32_e32 v5, s21, v6 -; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6 -; GFX6-NEXT: s_sub_u32 s0, 0, s8 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; GFX6-NEXT: v_mul_hi_u32 v4, s0, v5 -; GFX6-NEXT: v_mul_lo_u32 v7, s0, v6 -; GFX6-NEXT: s_subb_u32 s1, 0, s9 -; GFX6-NEXT: v_mul_lo_u32 v8, s1, v5 -; GFX6-NEXT: s_ashr_i32 s10, s3, 31 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GFX6-NEXT: v_mul_lo_u32 v7, s0, v5 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v8 -; GFX6-NEXT: v_mul_lo_u32 v8, v5, v4 -; GFX6-NEXT: v_mul_hi_u32 v9, v5, v7 -; GFX6-NEXT: v_mul_hi_u32 v10, v5, v4 -; GFX6-NEXT: v_mul_hi_u32 v11, v6, v4 -; GFX6-NEXT: v_mul_lo_u32 v4, v6, v4 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc -; GFX6-NEXT: v_mul_lo_u32 v10, v6, v7 -; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7 -; GFX6-NEXT: s_mov_b32 s11, s10 -; GFX6-NEXT: v_xor_b32_e32 v2, s14, v2 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc -; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_mul_lo_u32 v4, s6, v2 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GFX6-NEXT: v_mul_lo_u32 v7, v2, v3 +; GFX6-NEXT: v_mul_hi_u32 v8, v2, v4 +; GFX6-NEXT: v_mul_hi_u32 v9, v2, v3 +; GFX6-NEXT: v_mul_hi_u32 v6, v1, v4 +; GFX6-NEXT: v_mul_lo_u32 v4, v1, v4 +; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3 +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v7, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc +; GFX6-NEXT: v_mul_lo_u32 v3, s16, v1 +; GFX6-NEXT: v_mul_hi_u32 v4, s16, v2 +; GFX6-NEXT: v_mul_hi_u32 v5, s16, v1 +; GFX6-NEXT: v_mul_hi_u32 v6, s17, v1 +; GFX6-NEXT: v_mul_lo_u32 v1, s17, v1 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GFX6-NEXT: v_mul_lo_u32 v5, s17, v2 +; GFX6-NEXT: v_mul_hi_u32 v2, s17, v2 +; GFX6-NEXT: s_add_u32 s8, s8, s12 +; GFX6-NEXT: s_mov_b32 s13, s12 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc +; GFX6-NEXT: v_mul_lo_u32 v3, s10, v2 +; GFX6-NEXT: v_mul_hi_u32 v4, s10, v1 +; GFX6-NEXT: v_mul_lo_u32 v5, s11, v1 +; GFX6-NEXT: v_mov_b32_e32 v6, s11 +; GFX6-NEXT: s_addc_u32 s9, s9, s12 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_mul_lo_u32 v4, s10, v1 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s17, v3 +; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s16, v4 +; GFX6-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v6, vcc +; GFX6-NEXT: v_subrev_i32_e64 v6, s[0:1], s10, v4 +; GFX6-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1] +; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v5 +; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] +; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v6 +; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v5 +; GFX6-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1] +; GFX6-NEXT: v_add_i32_e64 v6, s[0:1], 2, v1 +; GFX6-NEXT: v_addc_u32_e64 v7, s[0:1], 0, v2, s[0:1] +; GFX6-NEXT: v_add_i32_e64 v8, s[0:1], 1, v1 +; GFX6-NEXT: v_addc_u32_e64 v9, s[0:1], 0, v2, s[0:1] +; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13] +; GFX6-NEXT: v_cndmask_b32_e64 v5, v9, v7, s[0:1] +; GFX6-NEXT: v_mov_b32_e32 v7, s17 +; GFX6-NEXT: v_cvt_f32_u32_e32 v9, s8 +; GFX6-NEXT: v_cvt_f32_u32_e32 v10, s9 +; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v7, v3, vcc +; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 +; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc +; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v4 +; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s11, v3 +; GFX6-NEXT: v_mac_f32_e32 v9, s18, v10 +; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v4, vcc +; GFX6-NEXT: v_rcp_f32_e32 v4, v9 +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v3, v8, v6, s[0:1] +; GFX6-NEXT: v_mul_f32_e32 v4, s19, v4 +; GFX6-NEXT: v_mul_f32_e32 v5, s20, v4 +; GFX6-NEXT: v_trunc_f32_e32 v5, v5 +; GFX6-NEXT: v_mac_f32_e32 v4, s21, v5 +; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4 +; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5 +; GFX6-NEXT: s_sub_u32 s0, 0, s8 +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX6-NEXT: v_mul_hi_u32 v3, s0, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, s0, v5 -; GFX6-NEXT: v_mul_hi_u32 v7, s0, v4 -; GFX6-NEXT: v_mul_lo_u32 v8, s1, v4 -; GFX6-NEXT: v_xor_b32_e32 v3, s15, v3 +; GFX6-NEXT: s_subb_u32 s1, 0, s9 +; GFX6-NEXT: v_mul_lo_u32 v7, s1, v4 +; GFX6-NEXT: s_ashr_i32 s10, s3, 31 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GFX6-NEXT: v_mul_lo_u32 v6, s0, v4 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; GFX6-NEXT: v_mul_lo_u32 v7, v4, v3 +; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6 +; GFX6-NEXT: v_mul_hi_u32 v9, v4, v3 +; GFX6-NEXT: v_mul_hi_u32 v10, v5, v3 +; GFX6-NEXT: v_mul_lo_u32 v3, v5, v3 +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GFX6-NEXT: v_mul_lo_u32 v9, v5, v6 +; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6 +; GFX6-NEXT: s_mov_b32 s11, s10 +; GFX6-NEXT: v_xor_b32_e32 v1, s14, v1 +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v8, v6, vcc +; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v10, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v5, v6, vcc +; GFX6-NEXT: v_mul_lo_u32 v5, s0, v4 +; GFX6-NEXT: v_mul_hi_u32 v6, s0, v3 +; GFX6-NEXT: v_mul_lo_u32 v7, s1, v3 +; GFX6-NEXT: v_xor_b32_e32 v2, s15, v2 ; GFX6-NEXT: s_mov_b32 s7, 0xf000 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_mul_lo_u32 v7, s0, v4 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GFX6-NEXT: v_mul_lo_u32 v10, v4, v6 -; GFX6-NEXT: v_mul_hi_u32 v11, v4, v7 -; GFX6-NEXT: v_mul_hi_u32 v12, v4, v6 -; GFX6-NEXT: v_mul_hi_u32 v9, v5, v7 -; GFX6-NEXT: v_mul_lo_u32 v7, v5, v7 -; GFX6-NEXT: v_mul_hi_u32 v8, v5, v6 -; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc -; GFX6-NEXT: v_mul_lo_u32 v6, v5, v6 -; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc -; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v8, v0, vcc -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GFX6-NEXT: v_mul_lo_u32 v6, s0, v3 +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GFX6-NEXT: v_mul_lo_u32 v9, v3, v5 +; GFX6-NEXT: v_mul_hi_u32 v10, v3, v6 +; GFX6-NEXT: v_mul_hi_u32 v11, v3, v5 +; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6 +; GFX6-NEXT: v_mul_lo_u32 v6, v4, v6 +; GFX6-NEXT: v_mul_hi_u32 v7, v4, v5 +; GFX6-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GFX6-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc +; GFX6-NEXT: v_mul_lo_u32 v5, v4, v5 +; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v10, v8, vcc +; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc ; GFX6-NEXT: s_add_u32 s0, s2, s10 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: s_addc_u32 s1, s3, s10 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc ; GFX6-NEXT: s_xor_b64 s[2:3], s[0:1], s[10:11] -; GFX6-NEXT: v_mul_lo_u32 v6, s2, v5 -; GFX6-NEXT: v_mul_hi_u32 v7, s2, v4 -; GFX6-NEXT: v_mul_hi_u32 v9, s2, v5 -; GFX6-NEXT: v_mul_hi_u32 v10, s3, v5 -; GFX6-NEXT: v_mul_lo_u32 v5, s3, v5 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc -; GFX6-NEXT: v_mul_lo_u32 v9, s3, v4 -; GFX6-NEXT: v_mul_hi_u32 v4, s3, v4 -; GFX6-NEXT: v_mov_b32_e32 v8, s15 +; GFX6-NEXT: v_mul_lo_u32 v5, s2, v4 +; GFX6-NEXT: v_mul_hi_u32 v6, s2, v3 +; GFX6-NEXT: v_mul_hi_u32 v8, s2, v4 +; GFX6-NEXT: v_mul_hi_u32 v9, s3, v4 +; GFX6-NEXT: v_mul_lo_u32 v4, s3, v4 +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; GFX6-NEXT: v_mul_lo_u32 v8, s3, v3 +; GFX6-NEXT: v_mul_hi_u32 v3, s3, v3 +; GFX6-NEXT: v_mov_b32_e32 v7, s15 ; GFX6-NEXT: s_mov_b32 s6, -1 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc -; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v0, vcc -; GFX6-NEXT: v_mul_lo_u32 v6, s8, v5 -; GFX6-NEXT: v_mul_hi_u32 v7, s8, v4 -; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s14, v2 -; GFX6-NEXT: v_mul_lo_u32 v2, s9, v4 -; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v3, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v7, v6 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_mul_lo_u32 v3, s8, v4 -; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s3, v2 +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc +; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v9, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v0, vcc +; GFX6-NEXT: v_mul_lo_u32 v5, s8, v4 +; GFX6-NEXT: v_mul_hi_u32 v6, s8, v3 +; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s14, v1 +; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v7, vcc +; GFX6-NEXT: v_mul_lo_u32 v2, s9, v3 +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 ; GFX6-NEXT: v_mov_b32_e32 v7, s9 -; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s2, v3 +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 +; GFX6-NEXT: v_mul_lo_u32 v5, s8, v3 +; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s3, v2 +; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s2, v5 ; GFX6-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc -; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s8, v3 +; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s8, v5 ; GFX6-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1] ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v6 ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] @@ -12335,25 +12316,25 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] ; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v6 ; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1] -; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v4 -; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v5, s[0:1] -; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v4 -; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v5, s[0:1] +; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v3 +; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v4, s[0:1] +; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 1, v3 +; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v4, s[0:1] ; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 ; GFX6-NEXT: v_cndmask_b32_e64 v6, v10, v8, s[0:1] ; GFX6-NEXT: v_mov_b32_e32 v8, s3 ; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v8, v2, vcc ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v2 ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v3 -; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v5 +; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s9, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v5, vcc ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GFX6-NEXT: v_cndmask_b32_e64 v3, v9, v7, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v4, v9, v7, s[0:1] +; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc ; GFX6-NEXT: s_xor_b64 s[0:1], s[10:11], s[12:13] -; GFX6-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc ; GFX6-NEXT: v_xor_b32_e32 v3, s0, v3 ; GFX6-NEXT: v_xor_b32_e32 v4, s1, v2 ; GFX6-NEXT: v_mov_b32_e32 v5, s1 @@ -12389,201 +12370,200 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1 -; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1 -; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0 +; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_ashr_i32 s14, s5, 31 ; GFX9-NEXT: s_mov_b32 s15, s14 -; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2 -; GFX9-NEXT: v_mul_hi_u32 v1, s2, v3 -; GFX9-NEXT: v_mul_lo_u32 v5, s3, v3 -; GFX9-NEXT: v_mul_lo_u32 v4, s2, v3 -; GFX9-NEXT: v_add_u32_e32 v0, v1, v0 -; GFX9-NEXT: v_add_u32_e32 v5, v0, v5 -; GFX9-NEXT: v_mul_hi_u32 v1, v3, v4 -; GFX9-NEXT: v_mul_lo_u32 v6, v3, v5 -; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5 -; GFX9-NEXT: v_mul_hi_u32 v8, v2, v5 -; GFX9-NEXT: v_mul_lo_u32 v5, v2, v5 -; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc -; GFX9-NEXT: v_mul_lo_u32 v7, v2, v4 -; GFX9-NEXT: v_mul_hi_u32 v4, v2, v4 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v8, v0, vcc -; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v6, vcc -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v5, vcc +; GFX9-NEXT: v_mul_lo_u32 v0, s2, v1 +; GFX9-NEXT: v_mul_hi_u32 v3, s2, v2 +; GFX9-NEXT: v_mul_lo_u32 v5, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, s2, v2 -; GFX9-NEXT: v_mul_hi_u32 v5, s2, v3 -; GFX9-NEXT: v_mul_lo_u32 v6, s3, v3 -; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3 -; GFX9-NEXT: s_add_u32 s2, s4, s14 -; GFX9-NEXT: v_add_u32_e32 v4, v5, v4 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v6 -; GFX9-NEXT: v_mul_lo_u32 v8, v3, v4 -; GFX9-NEXT: v_mul_hi_u32 v9, v3, v7 -; GFX9-NEXT: v_mul_hi_u32 v10, v3, v4 -; GFX9-NEXT: v_mul_hi_u32 v6, v2, v7 -; GFX9-NEXT: v_mul_lo_u32 v7, v2, v7 -; GFX9-NEXT: v_mul_hi_u32 v5, v2, v4 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc -; GFX9-NEXT: v_mul_lo_u32 v4, v2, v4 -; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v6, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v5, vcc +; GFX9-NEXT: v_add_u32_e32 v0, v3, v0 +; GFX9-NEXT: v_add_u32_e32 v5, v0, v5 +; GFX9-NEXT: v_mul_hi_u32 v3, v2, v4 +; GFX9-NEXT: v_mul_lo_u32 v6, v2, v5 +; GFX9-NEXT: v_mul_hi_u32 v7, v2, v5 +; GFX9-NEXT: v_mul_hi_u32 v8, v1, v5 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc +; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 +; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc +; GFX9-NEXT: v_mul_lo_u32 v4, v1, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v0, vcc ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc +; GFX9-NEXT: v_mul_lo_u32 v3, s2, v1 +; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2 +; GFX9-NEXT: v_mul_lo_u32 v5, s3, v2 +; GFX9-NEXT: v_mul_lo_u32 v6, s2, v2 +; GFX9-NEXT: s_add_u32 s2, s4, s14 +; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 +; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 +; GFX9-NEXT: v_mul_lo_u32 v7, v2, v3 +; GFX9-NEXT: v_mul_hi_u32 v8, v2, v6 +; GFX9-NEXT: v_mul_hi_u32 v9, v2, v3 +; GFX9-NEXT: v_mul_hi_u32 v5, v1, v6 +; GFX9-NEXT: v_mul_lo_u32 v6, v1, v6 +; GFX9-NEXT: v_mul_hi_u32 v4, v1, v3 +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc +; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3 +; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 ; GFX9-NEXT: s_addc_u32 s3, s5, s14 -; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX9-NEXT: s_xor_b64 s[4:5], s[2:3], s[14:15] -; GFX9-NEXT: v_mul_lo_u32 v4, s4, v2 -; GFX9-NEXT: v_mul_hi_u32 v5, s4, v3 -; GFX9-NEXT: v_mul_hi_u32 v6, s4, v2 -; GFX9-NEXT: v_mul_hi_u32 v7, s5, v2 -; GFX9-NEXT: v_mul_lo_u32 v2, s5, v2 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc -; GFX9-NEXT: v_mul_lo_u32 v6, s5, v3 -; GFX9-NEXT: v_mul_hi_u32 v3, s5, v3 +; GFX9-NEXT: v_mul_lo_u32 v3, s4, v1 +; GFX9-NEXT: v_mul_hi_u32 v4, s4, v2 +; GFX9-NEXT: v_mul_hi_u32 v5, s4, v1 +; GFX9-NEXT: v_mul_hi_u32 v6, s5, v1 +; GFX9-NEXT: v_mul_lo_u32 v1, s5, v1 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc +; GFX9-NEXT: v_mul_lo_u32 v5, s5, v2 +; GFX9-NEXT: v_mul_hi_u32 v2, s5, v2 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v4, vcc -; GFX9-NEXT: v_mul_lo_u32 v4, s10, v3 -; GFX9-NEXT: v_mul_hi_u32 v5, s10, v2 -; GFX9-NEXT: v_mul_lo_u32 v6, s11, v2 -; GFX9-NEXT: v_mov_b32_e32 v7, s11 -; GFX9-NEXT: v_add_u32_e32 v4, v5, v4 -; GFX9-NEXT: v_mul_lo_u32 v5, s10, v2 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v6 -; GFX9-NEXT: v_sub_u32_e32 v6, s5, v4 -; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, s4, v5 -; GFX9-NEXT: v_subb_co_u32_e64 v6, s[0:1], v6, v7, vcc -; GFX9-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s10, v5 -; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[0:1], 0, v6, s[0:1] -; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] -; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v7 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v4, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v2, v1 +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc +; GFX9-NEXT: v_mul_lo_u32 v3, s10, v2 +; GFX9-NEXT: v_mul_hi_u32 v4, s10, v1 +; GFX9-NEXT: v_mul_lo_u32 v5, s11, v1 +; GFX9-NEXT: v_mov_b32_e32 v6, s11 +; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 +; GFX9-NEXT: v_mul_lo_u32 v4, s10, v1 +; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 +; GFX9-NEXT: v_sub_u32_e32 v5, s5, v3 +; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s4, v4 +; GFX9-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc +; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s10, v4 +; GFX9-NEXT: v_subbrev_co_u32_e64 v5, s[0:1], 0, v5, s[0:1] +; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v5 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] -; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1] -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v6, 1, 2, s[0:1] -; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], v2, v6 -; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v3, s[0:1] +; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v6 +; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] +; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[0:1] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v5, 1, 2, s[0:1] +; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], v1, v5 +; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], 0, v2, s[0:1] ; GFX9-NEXT: s_xor_b64 s[0:1], s[14:15], s[12:13] ; GFX9-NEXT: s_ashr_i32 s4, s9, 31 ; GFX9-NEXT: s_add_u32 s8, s8, s4 -; GFX9-NEXT: v_mov_b32_e32 v8, s5 +; GFX9-NEXT: v_mov_b32_e32 v7, s5 ; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_addc_u32 s9, s9, s4 ; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[4:5] -; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v8, v4, vcc -; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s8 -; GFX9-NEXT: v_cvt_f32_u32_e32 v9, s9 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v4 -; GFX9-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v5 -; GFX9-NEXT: v_mac_f32_e32 v8, s16, v9 -; GFX9-NEXT: v_rcp_f32_e32 v8, v8 -; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v10, v5, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX9-NEXT: v_mul_f32_e32 v4, s17, v8 -; GFX9-NEXT: v_mul_f32_e32 v5, s18, v4 -; GFX9-NEXT: v_trunc_f32_e32 v5, v5 -; GFX9-NEXT: v_mac_f32_e32 v4, s19, v5 +; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc +; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s8 +; GFX9-NEXT: v_cvt_f32_u32_e32 v8, s9 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 +; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4 +; GFX9-NEXT: v_mac_f32_e32 v7, s16, v8 +; GFX9-NEXT: v_rcp_f32_e32 v7, v7 +; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v4, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 +; GFX9-NEXT: v_mul_f32_e32 v3, s17, v7 +; GFX9-NEXT: v_mul_f32_e32 v4, s18, v3 +; GFX9-NEXT: v_trunc_f32_e32 v4, v4 +; GFX9-NEXT: v_mac_f32_e32 v3, s19, v4 +; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX9-NEXT: s_sub_u32 s10, 0, s8 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc ; GFX9-NEXT: s_subb_u32 s11, 0, s9 -; GFX9-NEXT: v_mul_hi_u32 v6, s10, v4 -; GFX9-NEXT: v_mul_lo_u32 v8, s10, v5 -; GFX9-NEXT: v_mul_lo_u32 v9, s11, v4 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc +; GFX9-NEXT: v_mul_hi_u32 v5, s10, v3 ; GFX9-NEXT: v_mul_lo_u32 v7, s10, v4 -; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 -; GFX9-NEXT: v_add_u32_e32 v6, v6, v9 -; GFX9-NEXT: v_mul_lo_u32 v8, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v9, v4, v7 -; GFX9-NEXT: v_mul_hi_u32 v10, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v11, v5, v6 -; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc -; GFX9-NEXT: v_mul_lo_u32 v10, v5, v7 -; GFX9-NEXT: v_mul_hi_u32 v7, v5, v7 -; GFX9-NEXT: v_xor_b32_e32 v2, s0, v2 -; GFX9-NEXT: v_xor_b32_e32 v3, s1, v3 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v9, v7, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v8, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc -; GFX9-NEXT: v_mul_lo_u32 v6, s10, v5 -; GFX9-NEXT: v_mul_hi_u32 v7, s10, v4 -; GFX9-NEXT: v_mul_lo_u32 v8, s11, v4 -; GFX9-NEXT: v_mul_lo_u32 v9, s10, v4 +; GFX9-NEXT: v_mul_lo_u32 v8, s11, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc +; GFX9-NEXT: v_mul_lo_u32 v6, s10, v3 +; GFX9-NEXT: v_add_u32_e32 v5, v5, v7 +; GFX9-NEXT: v_add_u32_e32 v5, v5, v8 +; GFX9-NEXT: v_mul_lo_u32 v7, v3, v5 +; GFX9-NEXT: v_mul_hi_u32 v8, v3, v6 +; GFX9-NEXT: v_mul_hi_u32 v9, v3, v5 +; GFX9-NEXT: v_mul_hi_u32 v10, v4, v5 +; GFX9-NEXT: v_mul_lo_u32 v5, v4, v5 +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc +; GFX9-NEXT: v_mul_lo_u32 v9, v4, v6 +; GFX9-NEXT: v_mul_hi_u32 v6, v4, v6 +; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1 +; GFX9-NEXT: v_xor_b32_e32 v2, s1, v2 +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v8, v6, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v6, vcc +; GFX9-NEXT: v_mul_lo_u32 v5, s10, v4 +; GFX9-NEXT: v_mul_hi_u32 v6, s10, v3 +; GFX9-NEXT: v_mul_lo_u32 v7, s11, v3 +; GFX9-NEXT: v_mul_lo_u32 v8, s10, v3 ; GFX9-NEXT: s_ashr_i32 s10, s7, 31 -; GFX9-NEXT: v_add_u32_e32 v6, v7, v6 -; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 -; GFX9-NEXT: v_mul_lo_u32 v10, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v11, v4, v9 -; GFX9-NEXT: v_mul_hi_u32 v12, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v8, v5, v9 -; GFX9-NEXT: v_mul_lo_u32 v9, v5, v9 -; GFX9-NEXT: v_mul_hi_u32 v7, v5, v6 -; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc -; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 +; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 +; GFX9-NEXT: v_add_u32_e32 v5, v5, v7 +; GFX9-NEXT: v_mul_lo_u32 v9, v3, v5 +; GFX9-NEXT: v_mul_hi_u32 v10, v3, v8 +; GFX9-NEXT: v_mul_hi_u32 v11, v3, v5 +; GFX9-NEXT: v_mul_hi_u32 v7, v4, v8 +; GFX9-NEXT: v_mul_lo_u32 v8, v4, v8 +; GFX9-NEXT: v_mul_hi_u32 v6, v4, v5 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9 -; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v7, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc +; GFX9-NEXT: v_mul_lo_u32 v5, v4, v5 +; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v7, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc ; GFX9-NEXT: s_add_u32 s6, s6, s10 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: s_mov_b32 s11, s10 ; GFX9-NEXT: s_addc_u32 s7, s7, s10 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v6, vcc ; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11] -; GFX9-NEXT: v_mul_lo_u32 v6, s6, v5 -; GFX9-NEXT: v_mul_hi_u32 v7, s6, v4 -; GFX9-NEXT: v_mul_hi_u32 v9, s6, v5 -; GFX9-NEXT: v_mul_hi_u32 v10, s7, v5 -; GFX9-NEXT: v_mul_lo_u32 v5, s7, v5 -; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc -; GFX9-NEXT: v_mul_lo_u32 v9, s7, v4 -; GFX9-NEXT: v_mul_hi_u32 v4, s7, v4 -; GFX9-NEXT: v_mov_b32_e32 v8, s1 -; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v9 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v10, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v6, vcc -; GFX9-NEXT: v_mul_lo_u32 v6, s8, v5 -; GFX9-NEXT: v_mul_hi_u32 v7, s8, v4 -; GFX9-NEXT: v_mul_lo_u32 v9, s9, v4 -; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s0, v2 -; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v8, vcc -; GFX9-NEXT: v_add_u32_e32 v3, v7, v6 -; GFX9-NEXT: v_mul_lo_u32 v6, s8, v4 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v9 -; GFX9-NEXT: v_sub_u32_e32 v7, s7, v3 +; GFX9-NEXT: v_mul_lo_u32 v5, s6, v4 +; GFX9-NEXT: v_mul_hi_u32 v6, s6, v3 +; GFX9-NEXT: v_mul_hi_u32 v8, s6, v4 +; GFX9-NEXT: v_mul_hi_u32 v9, s7, v4 +; GFX9-NEXT: v_mul_lo_u32 v4, s7, v4 +; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc +; GFX9-NEXT: v_mul_lo_u32 v8, s7, v3 +; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3 +; GFX9-NEXT: v_mov_b32_e32 v7, s1 +; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc +; GFX9-NEXT: v_mul_lo_u32 v5, s8, v4 +; GFX9-NEXT: v_mul_hi_u32 v6, s8, v3 +; GFX9-NEXT: v_mul_lo_u32 v8, s9, v3 +; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s0, v1 +; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 +; GFX9-NEXT: v_mul_lo_u32 v6, s8, v3 +; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v7, vcc +; GFX9-NEXT: v_add_u32_e32 v5, v5, v8 +; GFX9-NEXT: v_sub_u32_e32 v7, s7, v5 ; GFX9-NEXT: v_mov_b32_e32 v8, s9 ; GFX9-NEXT: v_sub_co_u32_e32 v6, vcc, s6, v6 ; GFX9-NEXT: v_subb_co_u32_e64 v7, s[0:1], v7, v8, vcc @@ -12596,21 +12576,21 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX9-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v7 ; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v9, s7 -; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v9, v3, vcc -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 +; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v9, v5, vcc +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s9, v5 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s8, v6 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 1, 2, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3 -; GFX9-NEXT: v_add_co_u32_e64 v7, s[0:1], v4, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v6, vcc -; GFX9-NEXT: v_addc_co_u32_e64 v8, s[0:1], 0, v5, s[0:1] -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v7, vcc +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s9, v5 +; GFX9-NEXT: v_add_co_u32_e64 v7, s[0:1], v3, v7 +; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc +; GFX9-NEXT: v_addc_co_u32_e64 v8, s[0:1], 0, v4, s[0:1] +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc ; GFX9-NEXT: s_xor_b64 s[0:1], s[10:11], s[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v8, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX9-NEXT: v_xor_b32_e32 v3, s0, v3 ; GFX9-NEXT: v_xor_b32_e32 v4, s1, v4 ; GFX9-NEXT: v_mov_b32_e32 v5, s1 @@ -12672,9 +12652,8 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX90A-NEXT: v_mov_b32_e32 v6, 0 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, s0, v1 @@ -12683,20 +12662,20 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_mul_lo_u32 v3, s1, v0 ; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v0 -; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v2 +; GFX90A-NEXT: v_mul_hi_u32 v6, v1, v5 +; GFX90A-NEXT: v_mul_lo_u32 v7, v1, v5 +; GFX90A-NEXT: v_mul_lo_u32 v9, v0, v2 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5 -; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v2 -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10 -; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8 +; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v2 +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9 +; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v8, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX90A-NEXT: v_mul_hi_u32 v3, v1, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: s_add_u32 s0, s4, s14 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX90A-NEXT: s_addc_u32 s1, s5, s14 @@ -12707,15 +12686,15 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_mul_hi_u32 v2, s4, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc -; GFX90A-NEXT: v_mul_hi_u32 v7, s5, v0 +; GFX90A-NEXT: v_mul_hi_u32 v6, s5, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s5, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s5, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s5, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, s12, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s12, v0 ; GFX90A-NEXT: v_add_u32_e32 v2, v3, v2 @@ -12723,32 +12702,32 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, s12, v0 ; GFX90A-NEXT: v_sub_u32_e32 v3, s5, v2 -; GFX90A-NEXT: v_mov_b32_e32 v7, s13 +; GFX90A-NEXT: v_mov_b32_e32 v6, s13 ; GFX90A-NEXT: v_sub_co_u32_e32 v5, vcc, s4, v5 -; GFX90A-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v7, vcc -; GFX90A-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s12, v5 +; GFX90A-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v6, vcc +; GFX90A-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s12, v5 ; GFX90A-NEXT: v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1] ; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v3 -; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] -; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7 ; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] +; GFX90A-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v6 +; GFX90A-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] ; GFX90A-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v3 -; GFX90A-NEXT: v_cndmask_b32_e64 v3, v8, v7, s[0:1] +; GFX90A-NEXT: v_cndmask_b32_e64 v3, v7, v6, s[0:1] ; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 ; GFX90A-NEXT: v_cndmask_b32_e64 v3, 1, 2, s[0:1] -; GFX90A-NEXT: v_mov_b32_e32 v8, s5 +; GFX90A-NEXT: v_mov_b32_e32 v7, s5 ; GFX90A-NEXT: v_add_co_u32_e64 v3, s[0:1], v0, v3 -; GFX90A-NEXT: v_subb_co_u32_e32 v2, vcc, v8, v2, vcc -; GFX90A-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v1, s[0:1] +; GFX90A-NEXT: v_subb_co_u32_e32 v2, vcc, v7, v2, vcc +; GFX90A-NEXT: v_addc_co_u32_e64 v6, s[0:1], 0, v1, s[0:1] ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s13, v2 -; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc +; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s12, v5 ; GFX90A-NEXT: s_xor_b64 s[0:1], s[14:15], s[10:11] ; GFX90A-NEXT: s_ashr_i32 s4, s9, 31 ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, s13, v2 ; GFX90A-NEXT: s_add_u32 s8, s8, s4 -; GFX90A-NEXT: v_cndmask_b32_e32 v2, v8, v5, vcc +; GFX90A-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc ; GFX90A-NEXT: s_mov_b32 s5, s4 ; GFX90A-NEXT: s_addc_u32 s9, s9, s4 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 @@ -12757,7 +12736,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_cvt_f32_u32_e32 v2, s8 ; GFX90A-NEXT: v_cvt_f32_u32_e32 v3, s9 ; GFX90A-NEXT: v_xor_b32_e32 v0, s0, v0 -; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc +; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc ; GFX90A-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v0 ; GFX90A-NEXT: v_mac_f32_e32 v2, s16, v3 ; GFX90A-NEXT: v_rcp_f32_e32 v2, v2 @@ -12772,69 +12751,69 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX90A-NEXT: s_subb_u32 s1, 0, s9 ; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc -; GFX90A-NEXT: v_mul_hi_u32 v7, s0, v2 -; GFX90A-NEXT: v_mul_lo_u32 v8, s0, v3 +; GFX90A-NEXT: v_mul_hi_u32 v6, s0, v2 +; GFX90A-NEXT: v_mul_lo_u32 v7, s0, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, s1, v2 -; GFX90A-NEXT: v_add_u32_e32 v7, v7, v8 -; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5 -; GFX90A-NEXT: v_mul_lo_u32 v9, s0, v2 -; GFX90A-NEXT: v_mul_lo_u32 v8, v2, v5 -; GFX90A-NEXT: v_mul_hi_u32 v10, v2, v9 -; GFX90A-NEXT: v_mul_hi_u32 v7, v2, v5 -; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc -; GFX90A-NEXT: v_mul_hi_u32 v11, v3, v9 -; GFX90A-NEXT: v_mul_lo_u32 v9, v3, v9 -; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v9 -; GFX90A-NEXT: v_mul_hi_u32 v10, v3, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v11, vcc -; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v10, v4, vcc +; GFX90A-NEXT: v_add_u32_e32 v6, v6, v7 +; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5 +; GFX90A-NEXT: v_mul_lo_u32 v8, s0, v2 +; GFX90A-NEXT: v_mul_lo_u32 v7, v2, v5 +; GFX90A-NEXT: v_mul_hi_u32 v9, v2, v8 +; GFX90A-NEXT: v_mul_hi_u32 v6, v2, v5 +; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v9, v7 +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc +; GFX90A-NEXT: v_mul_hi_u32 v10, v3, v8 +; GFX90A-NEXT: v_mul_lo_u32 v8, v3, v8 +; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8 +; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v5 +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v10, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v9, v4, vcc +; GFX90A-NEXT: v_mul_lo_u32 v5, v3, v5 +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5 +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v6, vcc +; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v3 +; GFX90A-NEXT: v_mul_hi_u32 v6, s0, v2 +; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5 +; GFX90A-NEXT: v_mul_lo_u32 v6, s1, v2 +; GFX90A-NEXT: v_add_u32_e32 v5, v5, v6 +; GFX90A-NEXT: v_mul_lo_u32 v7, s0, v2 +; GFX90A-NEXT: v_mul_hi_u32 v8, v3, v7 +; GFX90A-NEXT: v_mul_lo_u32 v9, v3, v7 +; GFX90A-NEXT: v_mul_lo_u32 v11, v2, v5 +; GFX90A-NEXT: v_mul_hi_u32 v7, v2, v7 +; GFX90A-NEXT: v_mul_hi_u32 v10, v2, v5 +; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v11 +; GFX90A-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v10, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9 +; GFX90A-NEXT: v_mul_hi_u32 v6, v3, v5 +; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v8, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v5, v3, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v6, v8, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v7, vcc -; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v3 -; GFX90A-NEXT: v_mul_hi_u32 v7, s0, v2 -; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5 -; GFX90A-NEXT: v_mul_lo_u32 v7, s1, v2 -; GFX90A-NEXT: v_add_u32_e32 v5, v5, v7 -; GFX90A-NEXT: v_mul_lo_u32 v8, s0, v2 -; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v8 -; GFX90A-NEXT: v_mul_lo_u32 v10, v3, v8 -; GFX90A-NEXT: v_mul_lo_u32 v12, v2, v5 -; GFX90A-NEXT: v_mul_hi_u32 v8, v2, v8 -; GFX90A-NEXT: v_mul_hi_u32 v11, v2, v5 -; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12 -; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 -; GFX90A-NEXT: v_mul_hi_u32 v7, v3, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v4, vcc -; GFX90A-NEXT: v_mul_lo_u32 v5, v3, v5 -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v8, v5 ; GFX90A-NEXT: s_ashr_i32 s10, s7, 31 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v6, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc ; GFX90A-NEXT: s_add_u32 s0, s6, s10 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 ; GFX90A-NEXT: s_mov_b32 s11, s10 ; GFX90A-NEXT: s_addc_u32 s1, s7, s10 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v6, vcc ; GFX90A-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] -; GFX90A-NEXT: v_mul_lo_u32 v7, s6, v3 -; GFX90A-NEXT: v_mul_hi_u32 v8, s6, v2 +; GFX90A-NEXT: v_mul_lo_u32 v6, s6, v3 +; GFX90A-NEXT: v_mul_hi_u32 v7, s6, v2 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v3 -; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 +; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc -; GFX90A-NEXT: v_mul_hi_u32 v9, s7, v2 +; GFX90A-NEXT: v_mul_hi_u32 v8, s7, v2 ; GFX90A-NEXT: v_mul_lo_u32 v2, s7, v2 -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v7, v2 -; GFX90A-NEXT: v_mul_hi_u32 v8, s7, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v9, vcc -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2 +; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v3 +; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v8, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, s7, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX90A-NEXT: v_mul_lo_u32 v5, s8, v3 ; GFX90A-NEXT: v_mul_hi_u32 v6, s8, v2 ; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5 @@ -12894,85 +12873,84 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX6-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0 ; GFX6-NEXT: s_mov_b32 s4, 0xffed2705 -; GFX6-NEXT: v_mov_b32_e32 v8, 0 -; GFX6-NEXT: v_mov_b32_e32 v7, 0 +; GFX6-NEXT: v_mov_b32_e32 v5, 0 +; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GFX6-NEXT: s_mov_b32 s7, 0xf000 -; GFX6-NEXT: v_mul_lo_u32 v2, v1, s4 -; GFX6-NEXT: v_mul_hi_u32 v3, v0, s4 -; GFX6-NEXT: v_mul_lo_u32 v4, v0, s4 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_ashr_i32 s8, s3, 31 ; GFX6-NEXT: s_add_u32 s2, s2, s8 +; GFX6-NEXT: v_mul_lo_u32 v2, v1, s4 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, s4 +; GFX6-NEXT: v_mul_lo_u32 v4, v0, s4 +; GFX6-NEXT: s_mov_b32 s9, s8 +; GFX6-NEXT: s_addc_u32 s3, s3, s8 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 -; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v6, v0, v4 -; GFX6-NEXT: v_mul_hi_u32 v3, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v1, v2 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4 +; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v7, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc +; GFX6-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9] +; GFX6-NEXT: s_mov_b32 s5, s1 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v5, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s4 ; GFX6-NEXT: v_mul_hi_u32 v3, v0, s4 -; GFX6-NEXT: s_mov_b32 s9, s8 -; GFX6-NEXT: s_addc_u32 s3, s3, s8 -; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9] +; GFX6-NEXT: s_mov_b32 s7, 0xf000 +; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v3, v0, s4 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 -; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v10, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3 +; GFX6-NEXT: v_mul_lo_u32 v7, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v0, v3 +; GFX6-NEXT: v_mul_hi_u32 v9, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v9, v5, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v7, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v7, v3 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v6, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1 ; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0 ; GFX6-NEXT: v_mul_hi_u32 v4, s2, v1 -; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1 +; GFX6-NEXT: v_mul_hi_u32 v6, s3, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX6-NEXT: s_mov_b32 s4, s0 ; GFX6-NEXT: s_mov_b32 s0, 0x12d8fb ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v5, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s0 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, s0 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s0 -; GFX6-NEXT: s_mov_b32 s5, s1 -; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX6-NEXT: v_mov_b32_e32 v2, s3 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 @@ -13010,15 +12988,14 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: s_mov_b32 s4, 0xffed2705 -; GFX9-NEXT: v_mov_b32_e32 v7, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0 +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4 ; GFX9-NEXT: v_mul_hi_u32 v3, v0, s4 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s4 @@ -13027,17 +13004,17 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_mul_hi_u32 v3, v0, v4 ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v8, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v1, v2 -; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v7, v8, vcc -; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 +; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc +; GFX9-NEXT: v_mul_hi_u32 v8, v1, v2 +; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s4 @@ -13048,20 +13025,20 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: s_add_u32 s2, s2, s4 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_sub_u32_e32 v2, v2, v0 -; GFX9-NEXT: v_mul_lo_u32 v8, v0, v2 -; GFX9-NEXT: v_mul_hi_u32 v9, v0, v4 -; GFX9-NEXT: v_mul_hi_u32 v10, v0, v2 +; GFX9-NEXT: v_mul_lo_u32 v7, v0, v2 +; GFX9-NEXT: v_mul_hi_u32 v8, v0, v4 +; GFX9-NEXT: v_mul_hi_u32 v9, v0, v2 ; GFX9-NEXT: v_mul_hi_u32 v6, v1, v4 ; GFX9-NEXT: v_mul_lo_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v3, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v7, v10, vcc +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc ; GFX9-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v8, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v6, vcc +; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v7, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_addc_u32 s3, s3, s4 @@ -13073,7 +13050,7 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_mul_hi_u32 v6, s3, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v4, vcc ; GFX9-NEXT: v_mul_lo_u32 v4, s3, v0 ; GFX9-NEXT: v_mul_hi_u32 v0, s3, v0 ; GFX9-NEXT: s_mov_b32 s5, 0x12d8fb @@ -13081,7 +13058,7 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v0, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s5 ; GFX9-NEXT: v_mul_hi_u32 v2, v0, s5 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s5 @@ -13122,15 +13099,14 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_madak_f32 v0, 0, v0, 0x4996c7d8 ; GFX90A-NEXT: v_rcp_f32_e32 v0, v0 ; GFX90A-NEXT: s_mov_b32 s4, 0xffed2705 -; GFX90A-NEXT: v_mov_b32_e32 v8, 0 ; GFX90A-NEXT: v_mov_b32_e32 v2, 0 +; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX90A-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX90A-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX90A-NEXT: v_trunc_f32_e32 v1, v1 ; GFX90A-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX90A-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX90A-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s4 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, s4 ; GFX90A-NEXT: v_add_u32_e32 v3, v4, v3 @@ -13140,16 +13116,16 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_hi_u32 v7, v0, v6 ; GFX90A-NEXT: v_mul_hi_u32 v4, v0, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc -; GFX90A-NEXT: v_mul_hi_u32 v9, v1, v6 +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX90A-NEXT: v_mul_hi_u32 v8, v1, v6 ; GFX90A-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 ; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v9, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, s4 @@ -13159,20 +13135,20 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_lo_u32 v5, v0, s4 ; GFX90A-NEXT: v_mul_hi_u32 v6, v1, v5 ; GFX90A-NEXT: v_mul_lo_u32 v7, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v3 +; GFX90A-NEXT: v_mul_lo_u32 v9, v0, v3 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5 -; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v3 -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10 -; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, v8, v9, vcc +; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v3 +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9 +; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v8, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX90A-NEXT: v_mul_hi_u32 v4, v1, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v6, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 ; GFX90A-NEXT: s_waitcnt lgkmcnt(0) ; GFX90A-NEXT: s_ashr_i32 s4, s3, 31 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX90A-NEXT: s_add_u32 s2, s2, s4 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: s_mov_b32 s5, s4 @@ -13183,7 +13159,7 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_mul_hi_u32 v5, s2, v0 ; GFX90A-NEXT: v_mul_hi_u32 v3, s2, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: v_mul_hi_u32 v6, s3, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s3, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 @@ -13192,7 +13168,7 @@ define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) { ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s3, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v8, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX90A-NEXT: s_mov_b32 s5, 0x12d8fb ; GFX90A-NEXT: v_mul_lo_u32 v1, v1, s5 ; GFX90A-NEXT: v_mul_hi_u32 v3, v0, s5 @@ -13353,9 +13329,8 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc ; GFX6-NEXT: v_mov_b32_e32 v4, 0 ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v4, vcc -; GFX6-NEXT: v_mov_b32_e32 v6, 0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1 @@ -13365,26 +13340,26 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_mul_lo_u32 v3, s4, v0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v5, v2 -; GFX6-NEXT: v_mul_lo_u32 v8, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v9, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v10, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3 +; GFX6-NEXT: v_mul_lo_u32 v7, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v8, v0, v3 +; GFX6-NEXT: v_mul_hi_u32 v9, v0, v2 +; GFX6-NEXT: v_mul_hi_u32 v6, v1, v3 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_mul_hi_u32 v5, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v8, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v9, v7, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v7, v3 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, s12, v1 ; GFX6-NEXT: v_mul_hi_u32 v3, s12, v0 ; GFX6-NEXT: v_mul_hi_u32 v5, s12, v1 -; GFX6-NEXT: v_mul_hi_u32 v7, s13, v1 +; GFX6-NEXT: v_mul_hi_u32 v6, s13, v1 ; GFX6-NEXT: v_mul_lo_u32 v1, s13, v1 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc @@ -13393,9 +13368,9 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX6-NEXT: s_mov_b32 s4, s0 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v7, v4, vcc +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v6, v4, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GFX6-NEXT: v_mul_lo_u32 v1, s8, v1 ; GFX6-NEXT: v_mul_hi_u32 v2, s8, v0 ; GFX6-NEXT: v_mul_lo_u32 v3, s9, v0 @@ -13487,38 +13462,37 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v2, vcc -; GFX9-NEXT: v_mov_b32_e32 v6, 0 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX9-NEXT: v_mul_lo_u32 v3, s2, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s2, v0 ; GFX9-NEXT: v_mul_lo_u32 v5, s3, v0 -; GFX9-NEXT: v_mul_lo_u32 v7, s2, v0 +; GFX9-NEXT: v_mul_lo_u32 v6, s2, v0 ; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 -; GFX9-NEXT: v_mul_lo_u32 v8, v0, v3 -; GFX9-NEXT: v_mul_hi_u32 v9, v0, v7 -; GFX9-NEXT: v_mul_hi_u32 v10, v0, v3 -; GFX9-NEXT: v_mul_hi_u32 v5, v1, v7 -; GFX9-NEXT: v_mul_lo_u32 v7, v1, v7 +; GFX9-NEXT: v_mul_lo_u32 v7, v0, v3 +; GFX9-NEXT: v_mul_hi_u32 v8, v0, v6 +; GFX9-NEXT: v_mul_hi_u32 v9, v0, v3 +; GFX9-NEXT: v_mul_hi_u32 v5, v1, v6 +; GFX9-NEXT: v_mul_lo_u32 v6, v1, v6 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v3 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc -; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc +; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3 +; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX9-NEXT: v_mul_lo_u32 v3, s6, v1 ; GFX9-NEXT: v_mul_hi_u32 v4, s6, v0 ; GFX9-NEXT: v_mul_hi_u32 v5, s6, v1 -; GFX9-NEXT: v_mul_hi_u32 v7, s7, v1 +; GFX9-NEXT: v_mul_hi_u32 v6, s7, v1 ; GFX9-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc @@ -13526,9 +13500,9 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX9-NEXT: v_mul_hi_u32 v0, s7, v0 ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, v4, v0, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v2, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX9-NEXT: v_mul_lo_u32 v1, s8, v1 ; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0 ; GFX9-NEXT: v_mul_lo_u32 v4, s9, v0 @@ -13618,9 +13592,8 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 -; GFX90A-NEXT: v_mov_b32_e32 v6, 0 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, s0, v1 @@ -13629,20 +13602,20 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX90A-NEXT: v_mul_lo_u32 v4, s1, v0 ; GFX90A-NEXT: v_add_u32_e32 v3, v3, v4 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v0 -; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v3 +; GFX90A-NEXT: v_mul_hi_u32 v6, v1, v5 +; GFX90A-NEXT: v_mul_lo_u32 v7, v1, v5 +; GFX90A-NEXT: v_mul_lo_u32 v9, v0, v3 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5 -; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v3 -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10 -; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8 +; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v3 +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9 +; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v8, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX90A-NEXT: v_mul_hi_u32 v4, v1, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc ; GFX90A-NEXT: s_add_u32 s0, s6, s10 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v3 ; GFX90A-NEXT: s_addc_u32 s1, s7, s10 @@ -13653,15 +13626,15 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(i64 addrspace(1)* %out, i64 % ; GFX90A-NEXT: v_mul_hi_u32 v3, s6, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc -; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v0 +; GFX90A-NEXT: v_mul_hi_u32 v6, s7, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s7, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s7, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v3, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s7, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s8, v1 ; GFX90A-NEXT: v_mul_hi_u32 v3, s8, v0 ; GFX90A-NEXT: v_add_u32_e32 v1, v3, v1 @@ -13854,200 +13827,199 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX6-NEXT: v_mul_f32_e32 v1, s20, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, s21, v1 -; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1 -; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v0 +; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v0 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_ashr_i32 s12, s9, 31 ; GFX6-NEXT: s_add_u32 s0, s8, s12 -; GFX6-NEXT: v_mul_lo_u32 v0, s2, v2 -; GFX6-NEXT: v_mul_hi_u32 v1, s2, v3 -; GFX6-NEXT: v_mul_lo_u32 v4, s3, v3 -; GFX6-NEXT: v_mul_lo_u32 v5, s2, v3 +; GFX6-NEXT: v_mul_lo_u32 v0, s2, v1 +; GFX6-NEXT: v_mul_hi_u32 v3, s2, v2 +; GFX6-NEXT: v_mul_lo_u32 v4, s3, v2 +; GFX6-NEXT: v_mul_lo_u32 v5, s2, v2 ; GFX6-NEXT: s_mov_b32 s13, s12 -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0 -; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v4 -; GFX6-NEXT: v_mul_lo_u32 v0, v3, v1 -; GFX6-NEXT: v_mul_hi_u32 v4, v3, v5 -; GFX6-NEXT: v_mul_hi_u32 v6, v3, v1 -; GFX6-NEXT: v_mul_hi_u32 v7, v2, v1 -; GFX6-NEXT: s_addc_u32 s1, s9, s12 +; GFX6-NEXT: v_add_i32_e32 v0, vcc, v3, v0 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v0, v4 +; GFX6-NEXT: v_mul_lo_u32 v0, v2, v3 +; GFX6-NEXT: v_mul_hi_u32 v4, v2, v5 +; GFX6-NEXT: v_mul_hi_u32 v6, v2, v3 +; GFX6-NEXT: v_mul_hi_u32 v7, v1, v3 +; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0 ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc -; GFX6-NEXT: v_mul_lo_u32 v6, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v5, v2, v5 +; GFX6-NEXT: v_mul_lo_u32 v6, v1, v5 +; GFX6-NEXT: v_mul_hi_u32 v5, v1, v5 +; GFX6-NEXT: s_addc_u32 s1, s9, s12 ; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13] ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v6 ; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v5, vcc -; GFX6-NEXT: v_mul_lo_u32 v5, v2, v1 ; GFX6-NEXT: v_mov_b32_e32 v0, 0 -; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v7, v0, vcc -; GFX6-NEXT: v_mov_b32_e32 v1, 0 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v6, vcc -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s2, v2 -; GFX6-NEXT: v_mul_hi_u32 v5, s2, v3 -; GFX6-NEXT: v_mul_lo_u32 v6, s3, v3 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_mul_lo_u32 v5, s2, v3 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v6, v4 -; GFX6-NEXT: v_mul_lo_u32 v8, v3, v4 -; GFX6-NEXT: v_mul_hi_u32 v9, v3, v5 -; GFX6-NEXT: v_mul_hi_u32 v10, v3, v4 -; GFX6-NEXT: v_mul_hi_u32 v7, v2, v5 -; GFX6-NEXT: v_mul_lo_u32 v5, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v6, v2, v4 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, v2, v4 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v6, v0, vcc -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v1, v6, vcc -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s8, v2 -; GFX6-NEXT: v_mul_hi_u32 v5, s8, v3 -; GFX6-NEXT: v_mul_hi_u32 v6, s8, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, s9, v2 -; GFX6-NEXT: v_mul_lo_u32 v2, s9, v2 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc -; GFX6-NEXT: v_mul_lo_u32 v6, s9, v3 -; GFX6-NEXT: v_mul_hi_u32 v3, s9, v3 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v0, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v1, v4, vcc -; GFX6-NEXT: v_mul_lo_u32 v3, s16, v3 -; GFX6-NEXT: v_mul_hi_u32 v4, s16, v2 -; GFX6-NEXT: v_mul_lo_u32 v5, s17, v2 -; GFX6-NEXT: v_mul_lo_u32 v2, s16, v2 +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v0, vcc ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc +; GFX6-NEXT: v_mul_lo_u32 v3, s2, v1 +; GFX6-NEXT: v_mul_hi_u32 v4, s2, v2 +; GFX6-NEXT: v_mul_lo_u32 v5, s3, v2 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_mul_lo_u32 v4, s2, v2 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GFX6-NEXT: v_mul_lo_u32 v7, v2, v3 +; GFX6-NEXT: v_mul_hi_u32 v8, v2, v4 +; GFX6-NEXT: v_mul_hi_u32 v9, v2, v3 +; GFX6-NEXT: v_mul_hi_u32 v6, v1, v4 +; GFX6-NEXT: v_mul_lo_u32 v4, v1, v4 +; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3 +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 +; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc +; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc +; GFX6-NEXT: v_mul_lo_u32 v3, s8, v1 +; GFX6-NEXT: v_mul_hi_u32 v4, s8, v2 +; GFX6-NEXT: v_mul_hi_u32 v5, s8, v1 +; GFX6-NEXT: v_mul_hi_u32 v6, s9, v1 +; GFX6-NEXT: v_mul_lo_u32 v1, s9, v1 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GFX6-NEXT: v_mul_lo_u32 v5, s9, v2 +; GFX6-NEXT: v_mul_hi_u32 v2, s9, v2 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s9, v3 -; GFX6-NEXT: v_mov_b32_e32 v5, s17 -; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s8, v2 -; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc -; GFX6-NEXT: v_subrev_i32_e64 v6, s[0:1], s16, v2 -; GFX6-NEXT: v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s17, v7 +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc +; GFX6-NEXT: v_mul_lo_u32 v2, s16, v2 +; GFX6-NEXT: v_mul_hi_u32 v3, s16, v1 +; GFX6-NEXT: v_mul_lo_u32 v4, s17, v1 +; GFX6-NEXT: v_mul_lo_u32 v1, s16, v1 +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s9, v2 +; GFX6-NEXT: v_mov_b32_e32 v4, s17 +; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s8, v1 +; GFX6-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc +; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s16, v1 +; GFX6-NEXT: v_subbrev_u32_e64 v6, s[2:3], 0, v3, s[0:1] +; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s17, v6 +; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] +; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s16, v5 +; GFX6-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, s[0:1] ; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3] -; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s16, v6 -; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3] -; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s17, v7 -; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s16, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3] -; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] +; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s17, v6 +; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s16, v5 +; GFX6-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3] +; GFX6-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] ; GFX6-NEXT: s_ashr_i32 s2, s15, 31 -; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8 +; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 ; GFX6-NEXT: s_add_u32 s8, s14, s2 -; GFX6-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[0:1] -; GFX6-NEXT: v_mov_b32_e32 v7, s9 +; GFX6-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[0:1] +; GFX6-NEXT: v_mov_b32_e32 v6, s9 ; GFX6-NEXT: s_mov_b32 s3, s2 ; GFX6-NEXT: s_addc_u32 s9, s15, s2 ; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[2:3] -; GFX6-NEXT: v_cvt_f32_u32_e32 v8, s8 -; GFX6-NEXT: v_cvt_f32_u32_e32 v9, s9 -; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v7, v3, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s17, v3 -; GFX6-NEXT: v_mac_f32_e32 v8, s18, v9 -; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s16, v2 -; GFX6-NEXT: v_rcp_f32_e32 v8, v8 -; GFX6-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s17, v3 -; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 -; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc -; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] -; GFX6-NEXT: v_mul_f32_e32 v5, s19, v8 -; GFX6-NEXT: v_mul_f32_e32 v6, s20, v5 -; GFX6-NEXT: v_trunc_f32_e32 v6, v6 -; GFX6-NEXT: v_mac_f32_e32 v5, s21, v6 +; GFX6-NEXT: v_cvt_f32_u32_e32 v7, s8 +; GFX6-NEXT: v_cvt_f32_u32_e32 v8, s9 +; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc +; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s17, v2 +; GFX6-NEXT: v_mac_f32_e32 v7, s18, v8 +; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc +; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s16, v1 +; GFX6-NEXT: v_rcp_f32_e32 v7, v7 +; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc +; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s17, v2 +; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc +; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc +; GFX6-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1] +; GFX6-NEXT: v_mul_f32_e32 v4, s19, v7 +; GFX6-NEXT: v_mul_f32_e32 v5, s20, v4 +; GFX6-NEXT: v_trunc_f32_e32 v5, v5 +; GFX6-NEXT: v_mac_f32_e32 v4, s21, v5 +; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX6-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GFX6-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX6-NEXT: s_sub_u32 s0, 0, s8 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; GFX6-NEXT: v_mul_hi_u32 v4, s0, v5 -; GFX6-NEXT: v_mul_lo_u32 v7, s0, v6 -; GFX6-NEXT: s_subb_u32 s1, 0, s9 -; GFX6-NEXT: v_mul_lo_u32 v8, s1, v5 -; GFX6-NEXT: s_ashr_i32 s14, s11, 31 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GFX6-NEXT: v_mul_lo_u32 v7, s0, v5 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v8 -; GFX6-NEXT: v_mul_lo_u32 v8, v5, v4 -; GFX6-NEXT: v_mul_hi_u32 v9, v5, v7 -; GFX6-NEXT: v_mul_hi_u32 v10, v5, v4 -; GFX6-NEXT: v_mul_hi_u32 v11, v6, v4 -; GFX6-NEXT: v_mul_lo_u32 v4, v6, v4 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc -; GFX6-NEXT: v_mul_lo_u32 v10, v6, v7 -; GFX6-NEXT: v_mul_hi_u32 v7, v6, v7 -; GFX6-NEXT: s_mov_b32 s15, s14 -; GFX6-NEXT: v_xor_b32_e32 v2, s12, v2 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc -; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v11, v0, vcc -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v7, v4 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v6, v7, vcc +; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GFX6-NEXT: v_mul_hi_u32 v3, s0, v4 ; GFX6-NEXT: v_mul_lo_u32 v6, s0, v5 -; GFX6-NEXT: v_mul_hi_u32 v7, s0, v4 -; GFX6-NEXT: v_mul_lo_u32 v8, s1, v4 -; GFX6-NEXT: v_xor_b32_e32 v3, s12, v3 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_mul_lo_u32 v7, s0, v4 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v8, v6 -; GFX6-NEXT: v_mul_lo_u32 v10, v4, v6 -; GFX6-NEXT: v_mul_hi_u32 v11, v4, v7 -; GFX6-NEXT: v_mul_hi_u32 v12, v4, v6 -; GFX6-NEXT: v_mul_hi_u32 v9, v5, v7 -; GFX6-NEXT: v_mul_lo_u32 v7, v5, v7 -; GFX6-NEXT: v_mul_hi_u32 v8, v5, v6 -; GFX6-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GFX6-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc -; GFX6-NEXT: v_mul_lo_u32 v6, v5, v6 -; GFX6-NEXT: v_add_i32_e32 v7, vcc, v10, v7 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc -; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v8, v0, vcc -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v1, v8, vcc +; GFX6-NEXT: s_subb_u32 s1, 0, s9 +; GFX6-NEXT: v_mul_lo_u32 v7, s1, v4 +; GFX6-NEXT: s_ashr_i32 s14, s11, 31 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GFX6-NEXT: v_mul_lo_u32 v6, s0, v4 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; GFX6-NEXT: v_mul_lo_u32 v7, v4, v3 +; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6 +; GFX6-NEXT: v_mul_hi_u32 v9, v4, v3 +; GFX6-NEXT: v_mul_hi_u32 v10, v5, v3 +; GFX6-NEXT: v_mul_lo_u32 v3, v5, v3 +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GFX6-NEXT: v_mul_lo_u32 v9, v5, v6 +; GFX6-NEXT: v_mul_hi_u32 v6, v5, v6 +; GFX6-NEXT: s_mov_b32 s15, s14 +; GFX6-NEXT: v_xor_b32_e32 v1, s12, v1 +; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v9 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v8, v6, vcc +; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v10, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v5, v6, vcc +; GFX6-NEXT: v_mul_lo_u32 v5, s0, v4 +; GFX6-NEXT: v_mul_hi_u32 v6, s0, v3 +; GFX6-NEXT: v_mul_lo_u32 v7, s1, v3 +; GFX6-NEXT: v_xor_b32_e32 v2, s12, v2 +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GFX6-NEXT: v_mul_lo_u32 v6, s0, v3 +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GFX6-NEXT: v_mul_lo_u32 v9, v3, v5 +; GFX6-NEXT: v_mul_hi_u32 v10, v3, v6 +; GFX6-NEXT: v_mul_hi_u32 v11, v3, v5 +; GFX6-NEXT: v_mul_hi_u32 v8, v4, v6 +; GFX6-NEXT: v_mul_lo_u32 v6, v4, v6 +; GFX6-NEXT: v_mul_hi_u32 v7, v4, v5 +; GFX6-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GFX6-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc +; GFX6-NEXT: v_mul_lo_u32 v5, v4, v5 +; GFX6-NEXT: v_add_i32_e32 v6, vcc, v9, v6 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, v10, v8, vcc +; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc ; GFX6-NEXT: s_add_u32 s0, s10, s14 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GFX6-NEXT: s_addc_u32 s1, s11, s14 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc +; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc ; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15] -; GFX6-NEXT: v_mul_lo_u32 v6, s10, v5 -; GFX6-NEXT: v_mul_hi_u32 v7, s10, v4 -; GFX6-NEXT: v_mul_hi_u32 v9, s10, v5 -; GFX6-NEXT: v_mul_hi_u32 v10, s11, v5 -; GFX6-NEXT: v_mul_lo_u32 v5, s11, v5 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc -; GFX6-NEXT: v_mul_lo_u32 v9, s11, v4 -; GFX6-NEXT: v_mul_hi_u32 v4, s11, v4 -; GFX6-NEXT: v_mov_b32_e32 v8, s12 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v9 -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc -; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v10, v0, vcc -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v1, v0, vcc -; GFX6-NEXT: v_mul_lo_u32 v5, s8, v0 -; GFX6-NEXT: v_mul_hi_u32 v6, s8, v4 -; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v2 -; GFX6-NEXT: v_mul_lo_u32 v2, s9, v4 -; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v3, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v5 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_mul_lo_u32 v3, s8, v4 +; GFX6-NEXT: v_mul_lo_u32 v5, s10, v4 +; GFX6-NEXT: v_mul_hi_u32 v6, s10, v3 +; GFX6-NEXT: v_mul_hi_u32 v8, s10, v4 +; GFX6-NEXT: v_mul_hi_u32 v9, s11, v4 +; GFX6-NEXT: v_mul_lo_u32 v4, s11, v4 +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; GFX6-NEXT: v_mul_lo_u32 v8, s11, v3 +; GFX6-NEXT: v_mul_hi_u32 v3, s11, v3 +; GFX6-NEXT: v_mov_b32_e32 v7, s12 +; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v8 +; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v3, vcc +; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v9, v0, vcc +; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 +; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v0, vcc +; GFX6-NEXT: v_mul_lo_u32 v4, s8, v0 +; GFX6-NEXT: v_mul_hi_u32 v5, s8, v3 +; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v1 +; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v7, vcc +; GFX6-NEXT: v_mul_lo_u32 v2, s9, v3 +; GFX6-NEXT: v_mul_lo_u32 v3, s8, v3 +; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s11, v2 ; GFX6-NEXT: v_mov_b32_e32 v5, s9 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 @@ -14112,206 +14084,205 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX9-NEXT: v_mul_f32_e32 v1, s18, v0 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1 ; GFX9-NEXT: v_mac_f32_e32 v0, s19, v1 -; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1 -; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v0 +; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_ashr_i32 s8, s5, 31 ; GFX9-NEXT: s_mov_b32 s9, s8 -; GFX9-NEXT: v_mul_lo_u32 v0, s2, v2 -; GFX9-NEXT: v_mul_hi_u32 v1, s2, v3 -; GFX9-NEXT: v_mul_lo_u32 v5, s3, v3 -; GFX9-NEXT: v_mul_lo_u32 v4, s2, v3 -; GFX9-NEXT: v_add_u32_e32 v0, v1, v0 -; GFX9-NEXT: v_add_u32_e32 v5, v0, v5 -; GFX9-NEXT: v_mul_hi_u32 v1, v3, v4 -; GFX9-NEXT: v_mul_lo_u32 v6, v3, v5 -; GFX9-NEXT: v_mul_hi_u32 v7, v3, v5 -; GFX9-NEXT: v_mul_hi_u32 v8, v2, v5 -; GFX9-NEXT: v_mul_lo_u32 v5, v2, v5 -; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc -; GFX9-NEXT: v_mul_lo_u32 v7, v2, v4 -; GFX9-NEXT: v_mul_hi_u32 v4, v2, v4 -; GFX9-NEXT: v_mov_b32_e32 v0, 0 -; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v6, v4, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v8, v0, vcc -; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v6, vcc -; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v5, vcc +; GFX9-NEXT: v_mul_lo_u32 v0, s2, v1 +; GFX9-NEXT: v_mul_hi_u32 v3, s2, v2 +; GFX9-NEXT: v_mul_lo_u32 v5, s3, v2 ; GFX9-NEXT: v_mul_lo_u32 v4, s2, v2 -; GFX9-NEXT: v_mul_hi_u32 v5, s2, v3 -; GFX9-NEXT: v_mul_lo_u32 v6, s3, v3 -; GFX9-NEXT: v_mul_lo_u32 v7, s2, v3 -; GFX9-NEXT: s_add_u32 s2, s4, s8 -; GFX9-NEXT: v_add_u32_e32 v4, v5, v4 -; GFX9-NEXT: v_add_u32_e32 v4, v4, v6 -; GFX9-NEXT: v_mul_lo_u32 v8, v3, v4 -; GFX9-NEXT: v_mul_hi_u32 v9, v3, v7 -; GFX9-NEXT: v_mul_hi_u32 v10, v3, v4 -; GFX9-NEXT: v_mul_hi_u32 v6, v2, v7 -; GFX9-NEXT: v_mul_lo_u32 v7, v2, v7 -; GFX9-NEXT: v_mul_hi_u32 v5, v2, v4 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc -; GFX9-NEXT: v_mul_lo_u32 v4, v2, v4 -; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v6, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v6, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v1, v5, vcc +; GFX9-NEXT: v_add_u32_e32 v0, v3, v0 +; GFX9-NEXT: v_add_u32_e32 v5, v0, v5 +; GFX9-NEXT: v_mul_hi_u32 v3, v2, v4 +; GFX9-NEXT: v_mul_lo_u32 v6, v2, v5 +; GFX9-NEXT: v_mul_hi_u32 v7, v2, v5 +; GFX9-NEXT: v_mul_hi_u32 v8, v1, v5 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc +; GFX9-NEXT: v_mul_lo_u32 v7, v1, v4 +; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v7 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v4, vcc +; GFX9-NEXT: v_mul_lo_u32 v4, v1, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v0, vcc ; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 -; GFX9-NEXT: s_addc_u32 s3, s5, s8 -; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v2, v5, vcc -; GFX9-NEXT: s_xor_b64 s[14:15], s[2:3], s[8:9] -; GFX9-NEXT: v_mul_lo_u32 v4, s14, v2 -; GFX9-NEXT: v_mul_hi_u32 v5, s14, v3 -; GFX9-NEXT: v_mul_hi_u32 v6, s14, v2 -; GFX9-NEXT: v_mul_hi_u32 v7, s15, v2 -; GFX9-NEXT: v_mul_lo_u32 v2, s15, v2 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc -; GFX9-NEXT: v_mul_lo_u32 v6, s15, v3 -; GFX9-NEXT: v_mul_hi_u32 v3, s15, v3 -; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v1, v4, vcc -; GFX9-NEXT: v_mul_lo_u32 v3, s12, v3 -; GFX9-NEXT: v_mul_hi_u32 v4, s12, v2 -; GFX9-NEXT: v_mul_lo_u32 v5, s13, v2 -; GFX9-NEXT: v_mul_lo_u32 v2, s12, v2 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc +; GFX9-NEXT: v_mul_lo_u32 v3, s2, v1 +; GFX9-NEXT: v_mul_hi_u32 v4, s2, v2 +; GFX9-NEXT: v_mul_lo_u32 v5, s3, v2 +; GFX9-NEXT: v_mul_lo_u32 v6, s2, v2 +; GFX9-NEXT: s_add_u32 s2, s4, s8 ; GFX9-NEXT: v_add_u32_e32 v3, v4, v3 ; GFX9-NEXT: v_add_u32_e32 v3, v3, v5 -; GFX9-NEXT: v_sub_u32_e32 v4, s15, v3 -; GFX9-NEXT: v_mov_b32_e32 v5, s13 -; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s14, v2 -; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v5, vcc -; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s12, v2 -; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[2:3], 0, v4, s[0:1] -; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v7 +; GFX9-NEXT: v_mul_lo_u32 v7, v2, v3 +; GFX9-NEXT: v_mul_hi_u32 v8, v2, v6 +; GFX9-NEXT: v_mul_hi_u32 v9, v2, v3 +; GFX9-NEXT: v_mul_hi_u32 v5, v1, v6 +; GFX9-NEXT: v_mul_lo_u32 v6, v1, v6 +; GFX9-NEXT: v_mul_hi_u32 v4, v1, v3 +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc +; GFX9-NEXT: v_mul_lo_u32 v3, v1, v3 +; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v5, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc +; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 +; GFX9-NEXT: s_addc_u32 s3, s5, s8 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc +; GFX9-NEXT: s_xor_b64 s[14:15], s[2:3], s[8:9] +; GFX9-NEXT: v_mul_lo_u32 v3, s14, v1 +; GFX9-NEXT: v_mul_hi_u32 v4, s14, v2 +; GFX9-NEXT: v_mul_hi_u32 v5, s14, v1 +; GFX9-NEXT: v_mul_hi_u32 v6, s15, v1 +; GFX9-NEXT: v_mul_lo_u32 v1, s15, v1 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc +; GFX9-NEXT: v_mul_lo_u32 v5, s15, v2 +; GFX9-NEXT: v_mul_hi_u32 v2, s15, v2 +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v4, v2, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v2, v1 +; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v3, vcc +; GFX9-NEXT: v_mul_lo_u32 v2, s12, v2 +; GFX9-NEXT: v_mul_hi_u32 v3, s12, v1 +; GFX9-NEXT: v_mul_lo_u32 v4, s13, v1 +; GFX9-NEXT: v_mul_lo_u32 v1, s12, v1 +; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 +; GFX9-NEXT: v_add_u32_e32 v2, v2, v4 +; GFX9-NEXT: v_sub_u32_e32 v3, s15, v2 +; GFX9-NEXT: v_mov_b32_e32 v4, s13 +; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, s14, v1 +; GFX9-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v4, vcc +; GFX9-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s12, v1 +; GFX9-NEXT: v_subbrev_co_u32_e64 v6, s[2:3], 0, v3, s[0:1] +; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v6 +; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] +; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v5 +; GFX9-NEXT: v_subb_co_u32_e64 v3, s[0:1], v3, v4, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3] -; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v6 -; GFX9-NEXT: v_subb_co_u32_e64 v4, s[0:1], v4, v5, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3] -; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v7 -; GFX9-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s12, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3] -; GFX9-NEXT: v_subbrev_co_u32_e64 v4, s[0:1], 0, v4, s[0:1] -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8 -; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v5, s[0:1] -; GFX9-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[0:1] +; GFX9-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v6 +; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[0:1], s12, v5 +; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3] +; GFX9-NEXT: v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 +; GFX9-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[0:1] +; GFX9-NEXT: v_cndmask_b32_e64 v3, v6, v3, s[0:1] ; GFX9-NEXT: s_ashr_i32 s0, s11, 31 ; GFX9-NEXT: s_add_u32 s2, s10, s0 ; GFX9-NEXT: s_mov_b32 s1, s0 ; GFX9-NEXT: s_addc_u32 s3, s11, s0 -; GFX9-NEXT: v_mov_b32_e32 v6, s15 +; GFX9-NEXT: v_mov_b32_e32 v5, s15 ; GFX9-NEXT: s_xor_b64 s[10:11], s[2:3], s[0:1] -; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v6, v3, vcc -; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s10 -; GFX9-NEXT: v_cvt_f32_u32_e32 v7, s11 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v3 +; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v5, v2, vcc +; GFX9-NEXT: v_cvt_f32_u32_e32 v5, s10 +; GFX9-NEXT: v_cvt_f32_u32_e32 v6, s11 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s13, v2 +; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v1 +; GFX9-NEXT: v_mac_f32_e32 v5, s16, v6 +; GFX9-NEXT: v_rcp_f32_e32 v5, v5 ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v2 -; GFX9-NEXT: v_mac_f32_e32 v6, s16, v7 -; GFX9-NEXT: v_rcp_f32_e32 v6, v6 -; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s13, v3 -; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX9-NEXT: v_mul_f32_e32 v5, s17, v6 -; GFX9-NEXT: v_mul_f32_e32 v6, s18, v5 -; GFX9-NEXT: v_trunc_f32_e32 v6, v6 -; GFX9-NEXT: v_mac_f32_e32 v5, s19, v6 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s13, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc +; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GFX9-NEXT: v_mul_f32_e32 v4, s17, v5 +; GFX9-NEXT: v_mul_f32_e32 v5, s18, v4 +; GFX9-NEXT: v_trunc_f32_e32 v5, v5 +; GFX9-NEXT: v_mac_f32_e32 v4, s19, v5 +; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 -; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX9-NEXT: s_sub_u32 s0, 0, s10 ; GFX9-NEXT: s_subb_u32 s1, 0, s11 -; GFX9-NEXT: v_mul_hi_u32 v7, s0, v5 -; GFX9-NEXT: v_mul_lo_u32 v8, s0, v6 -; GFX9-NEXT: v_mul_lo_u32 v9, s1, v5 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc -; GFX9-NEXT: v_mul_lo_u32 v4, s0, v5 -; GFX9-NEXT: v_add_u32_e32 v7, v7, v8 -; GFX9-NEXT: v_add_u32_e32 v7, v7, v9 -; GFX9-NEXT: v_mul_lo_u32 v8, v5, v7 -; GFX9-NEXT: v_mul_hi_u32 v9, v5, v4 -; GFX9-NEXT: v_mul_hi_u32 v10, v5, v7 -; GFX9-NEXT: v_mul_hi_u32 v11, v6, v7 -; GFX9-NEXT: v_mul_lo_u32 v7, v6, v7 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc -; GFX9-NEXT: v_mul_lo_u32 v10, v6, v4 -; GFX9-NEXT: v_mul_hi_u32 v4, v6, v4 +; GFX9-NEXT: v_mul_hi_u32 v6, s0, v4 +; GFX9-NEXT: v_mul_lo_u32 v7, s0, v5 +; GFX9-NEXT: v_mul_lo_u32 v8, s1, v4 +; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc +; GFX9-NEXT: v_mul_lo_u32 v3, s0, v4 +; GFX9-NEXT: v_add_u32_e32 v6, v6, v7 +; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 +; GFX9-NEXT: v_mul_lo_u32 v7, v4, v6 +; GFX9-NEXT: v_mul_hi_u32 v8, v4, v3 +; GFX9-NEXT: v_mul_hi_u32 v9, v4, v6 +; GFX9-NEXT: v_mul_hi_u32 v10, v5, v6 +; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc +; GFX9-NEXT: v_mul_lo_u32 v9, v5, v3 +; GFX9-NEXT: v_mul_hi_u32 v3, v5, v3 ; GFX9-NEXT: s_ashr_i32 s12, s7, 31 ; GFX9-NEXT: s_mov_b32 s13, s12 -; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v9, v4, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v8, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v5, v4 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v6, v7, vcc -; GFX9-NEXT: v_mul_lo_u32 v6, s0, v5 -; GFX9-NEXT: v_mul_hi_u32 v7, s0, v4 -; GFX9-NEXT: v_mul_lo_u32 v8, s1, v4 -; GFX9-NEXT: v_mul_lo_u32 v9, s0, v4 +; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v4, v3 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v5, v6, vcc +; GFX9-NEXT: v_mul_lo_u32 v5, s0, v4 +; GFX9-NEXT: v_mul_hi_u32 v6, s0, v3 +; GFX9-NEXT: v_mul_lo_u32 v7, s1, v3 +; GFX9-NEXT: v_mul_lo_u32 v8, s0, v3 ; GFX9-NEXT: s_add_u32 s0, s6, s12 -; GFX9-NEXT: v_add_u32_e32 v6, v7, v6 -; GFX9-NEXT: v_add_u32_e32 v6, v6, v8 -; GFX9-NEXT: v_mul_lo_u32 v10, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v11, v4, v9 -; GFX9-NEXT: v_mul_hi_u32 v12, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v8, v5, v9 -; GFX9-NEXT: v_mul_lo_u32 v9, v5, v9 -; GFX9-NEXT: v_mul_hi_u32 v7, v5, v6 -; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc -; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 +; GFX9-NEXT: v_add_u32_e32 v5, v6, v5 +; GFX9-NEXT: v_add_u32_e32 v5, v5, v7 +; GFX9-NEXT: v_mul_lo_u32 v9, v3, v5 +; GFX9-NEXT: v_mul_hi_u32 v10, v3, v8 +; GFX9-NEXT: v_mul_hi_u32 v11, v3, v5 +; GFX9-NEXT: v_mul_hi_u32 v7, v4, v8 +; GFX9-NEXT: v_mul_lo_u32 v8, v4, v8 +; GFX9-NEXT: v_mul_hi_u32 v6, v4, v5 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9 -; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v8, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v8, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v1, v7, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc +; GFX9-NEXT: v_mul_lo_u32 v5, v4, v5 +; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v7, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 ; GFX9-NEXT: s_addc_u32 s1, s7, s12 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v6, vcc ; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13] -; GFX9-NEXT: v_mul_lo_u32 v6, s6, v5 -; GFX9-NEXT: v_mul_hi_u32 v7, s6, v4 -; GFX9-NEXT: v_mul_hi_u32 v9, s6, v5 -; GFX9-NEXT: v_mul_hi_u32 v10, s7, v5 -; GFX9-NEXT: v_mul_lo_u32 v5, s7, v5 -; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v9, vcc -; GFX9-NEXT: v_mul_lo_u32 v9, s7, v4 -; GFX9-NEXT: v_mul_hi_u32 v4, s7, v4 +; GFX9-NEXT: v_mul_lo_u32 v5, s6, v4 +; GFX9-NEXT: v_mul_hi_u32 v6, s6, v3 +; GFX9-NEXT: v_mul_hi_u32 v8, s6, v4 +; GFX9-NEXT: v_mul_hi_u32 v9, s7, v4 +; GFX9-NEXT: v_mul_lo_u32 v4, s7, v4 +; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5 +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc +; GFX9-NEXT: v_mul_lo_u32 v8, s7, v3 +; GFX9-NEXT: v_mul_hi_u32 v3, s7, v3 +; GFX9-NEXT: v_xor_b32_e32 v1, s8, v1 ; GFX9-NEXT: v_xor_b32_e32 v2, s8, v2 -; GFX9-NEXT: v_xor_b32_e32 v3, s8, v3 -; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v9 -; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v10, v0, vcc -; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v6, vcc -; GFX9-NEXT: v_mul_lo_u32 v5, s10, v1 -; GFX9-NEXT: v_mul_hi_u32 v6, s10, v4 -; GFX9-NEXT: v_mul_lo_u32 v7, s11, v4 +; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8 +; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v0, vcc +; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 +; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc ; GFX9-NEXT: v_mul_lo_u32 v4, s10, v4 -; GFX9-NEXT: v_mov_b32_e32 v8, s8 -; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s8, v2 -; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v8, vcc -; GFX9-NEXT: v_add_u32_e32 v3, v6, v5 -; GFX9-NEXT: v_add_u32_e32 v3, v3, v7 -; GFX9-NEXT: v_sub_u32_e32 v5, s7, v3 +; GFX9-NEXT: v_mul_hi_u32 v5, s10, v3 +; GFX9-NEXT: v_mul_lo_u32 v6, s11, v3 +; GFX9-NEXT: v_mul_lo_u32 v3, s10, v3 +; GFX9-NEXT: v_mov_b32_e32 v7, s8 +; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s8, v1 +; GFX9-NEXT: v_add_u32_e32 v4, v5, v4 +; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v7, vcc +; GFX9-NEXT: v_add_u32_e32 v4, v4, v6 +; GFX9-NEXT: v_sub_u32_e32 v5, s7, v4 ; GFX9-NEXT: v_mov_b32_e32 v6, s11 -; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s6, v4 +; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, s6, v3 ; GFX9-NEXT: v_subb_co_u32_e64 v5, s[0:1], v5, v6, vcc -; GFX9-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s10, v4 +; GFX9-NEXT: v_subrev_co_u32_e64 v7, s[0:1], s10, v3 ; GFX9-NEXT: v_subbrev_co_u32_e64 v8, s[2:3], 0, v5, s[0:1] ; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s11, v8 ; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3] @@ -14325,22 +14296,22 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v9 ; GFX9-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v7, s7 -; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v7, v3, vcc -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v3 +; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v7, v4, vcc +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s11, v4 ; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v4 +; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 ; GFX9-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v3 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s11, v4 ; GFX9-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc +; GFX9-NEXT: v_xor_b32_e32 v3, s12, v3 ; GFX9-NEXT: v_xor_b32_e32 v4, s12, v4 -; GFX9-NEXT: v_xor_b32_e32 v5, s12, v3 -; GFX9-NEXT: v_mov_b32_e32 v6, s12 -; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s12, v4 -; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v5, v6, vcc +; GFX9-NEXT: v_mov_b32_e32 v5, s12 +; GFX9-NEXT: v_subrev_co_u32_e32 v3, vcc, s12, v3 +; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v4, v5, vcc ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[4:5] ; GFX9-NEXT: s_endpgm @@ -14397,9 +14368,8 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX90A-NEXT: v_mov_b32_e32 v6, 0 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v3, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, s0, v1 @@ -14408,20 +14378,20 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_mul_lo_u32 v3, s1, v0 ; GFX90A-NEXT: v_add_u32_e32 v2, v2, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v0 -; GFX90A-NEXT: v_mul_hi_u32 v7, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v8, v1, v5 -; GFX90A-NEXT: v_mul_lo_u32 v10, v0, v2 +; GFX90A-NEXT: v_mul_hi_u32 v6, v1, v5 +; GFX90A-NEXT: v_mul_lo_u32 v7, v1, v5 +; GFX90A-NEXT: v_mul_lo_u32 v9, v0, v2 ; GFX90A-NEXT: v_mul_hi_u32 v5, v0, v5 -; GFX90A-NEXT: v_mul_hi_u32 v9, v0, v2 -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v10 -; GFX90A-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v9, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v8 +; GFX90A-NEXT: v_mul_hi_u32 v8, v0, v2 +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9 +; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v8, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX90A-NEXT: v_mul_hi_u32 v3, v1, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v2, v1, v2 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v5, v2 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v3, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX90A-NEXT: s_add_u32 s0, s4, s14 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; GFX90A-NEXT: s_addc_u32 s1, s5, s14 @@ -14432,15 +14402,15 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_mul_hi_u32 v2, s4, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v3, vcc, v5, v3 ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc -; GFX90A-NEXT: v_mul_hi_u32 v7, s5, v0 +; GFX90A-NEXT: v_mul_hi_u32 v6, s5, v0 ; GFX90A-NEXT: v_mul_lo_u32 v0, s5, v0 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v3, v0 ; GFX90A-NEXT: v_mul_hi_u32 v5, s5, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v0, vcc, v2, v6, vcc ; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s5, v1 ; GFX90A-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 -; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v2, vcc ; GFX90A-NEXT: v_mul_lo_u32 v1, s12, v1 ; GFX90A-NEXT: v_mul_hi_u32 v2, s12, v0 ; GFX90A-NEXT: v_add_u32_e32 v1, v2, v1 @@ -14452,29 +14422,29 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_sub_co_u32_e32 v0, vcc, s4, v0 ; GFX90A-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, vcc ; GFX90A-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s12, v0 -; GFX90A-NEXT: v_subbrev_co_u32_e64 v7, s[2:3], 0, v2, s[0:1] -; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v7 -; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3] +; GFX90A-NEXT: v_subbrev_co_u32_e64 v6, s[2:3], 0, v2, s[0:1] +; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v6 +; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] ; GFX90A-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v5 ; GFX90A-NEXT: v_subb_co_u32_e64 v2, s[0:1], v2, v3, s[0:1] -; GFX90A-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3] -; GFX90A-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v7 +; GFX90A-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3] +; GFX90A-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v6 ; GFX90A-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s12, v5 -; GFX90A-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3] +; GFX90A-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[2:3] ; GFX90A-NEXT: v_subbrev_co_u32_e64 v2, s[0:1], 0, v2, s[0:1] -; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8 +; GFX90A-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v7 ; GFX90A-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[0:1] ; GFX90A-NEXT: v_mov_b32_e32 v5, s5 ; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v5, v1, vcc ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s13, v1 -; GFX90A-NEXT: v_cndmask_b32_e64 v2, v7, v2, s[0:1] +; GFX90A-NEXT: v_cndmask_b32_e64 v2, v6, v2, s[0:1] ; GFX90A-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; GFX90A-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 ; GFX90A-NEXT: s_ashr_i32 s0, s11, 31 -; GFX90A-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc +; GFX90A-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1 ; GFX90A-NEXT: s_add_u32 s2, s10, s0 -; GFX90A-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc +; GFX90A-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc ; GFX90A-NEXT: s_mov_b32 s1, s0 ; GFX90A-NEXT: s_addc_u32 s3, s11, s0 ; GFX90A-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 @@ -14498,69 +14468,69 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %ou ; GFX90A-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX90A-NEXT: s_subb_u32 s1, 0, s5 ; GFX90A-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc -; GFX90A-NEXT: v_mul_hi_u32 v7, s0, v2 -; GFX90A-NEXT: v_mul_lo_u32 v8, s0, v3 +; GFX90A-NEXT: v_mul_hi_u32 v6, s0, v2 +; GFX90A-NEXT: v_mul_lo_u32 v7, s0, v3 ; GFX90A-NEXT: v_mul_lo_u32 v5, s1, v2 -; GFX90A-NEXT: v_add_u32_e32 v7, v7, v8 -; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5 -; GFX90A-NEXT: v_mul_lo_u32 v9, s0, v2 -; GFX90A-NEXT: v_mul_lo_u32 v8, v2, v5 -; GFX90A-NEXT: v_mul_hi_u32 v10, v2, v9 -; GFX90A-NEXT: v_mul_hi_u32 v7, v2, v5 -; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v10, v8 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v7, vcc -; GFX90A-NEXT: v_mul_hi_u32 v11, v3, v9 -; GFX90A-NEXT: v_mul_lo_u32 v9, v3, v9 -; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v9 -; GFX90A-NEXT: v_mul_hi_u32 v10, v3, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v11, vcc -; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v10, v4, vcc +; GFX90A-NEXT: v_add_u32_e32 v6, v6, v7 +; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5 +; GFX90A-NEXT: v_mul_lo_u32 v8, s0, v2 +; GFX90A-NEXT: v_mul_lo_u32 v7, v2, v5 +; GFX90A-NEXT: v_mul_hi_u32 v9, v2, v8 +; GFX90A-NEXT: v_mul_hi_u32 v6, v2, v5 +; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v9, v7 +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc +; GFX90A-NEXT: v_mul_hi_u32 v10, v3, v8 +; GFX90A-NEXT: v_mul_lo_u32 v8, v3, v8 +; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8 +; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v5 +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v10, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v9, v4, vcc +; GFX90A-NEXT: v_mul_lo_u32 v5, v3, v5 +; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v6, v5 +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v7, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v6, vcc +; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v3 +; GFX90A-NEXT: v_mul_hi_u32 v6, s0, v2 +; GFX90A-NEXT: v_add_u32_e32 v5, v6, v5 +; GFX90A-NEXT: v_mul_lo_u32 v6, s1, v2 +; GFX90A-NEXT: v_add_u32_e32 v5, v5, v6 +; GFX90A-NEXT: v_mul_lo_u32 v7, s0, v2 +; GFX90A-NEXT: v_mul_hi_u32 v8, v3, v7 +; GFX90A-NEXT: v_mul_lo_u32 v9, v3, v7 +; GFX90A-NEXT: v_mul_lo_u32 v11, v2, v5 +; GFX90A-NEXT: v_mul_hi_u32 v7, v2, v7 +; GFX90A-NEXT: v_mul_hi_u32 v10, v2, v5 +; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v11 +; GFX90A-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v10, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v7, v9 +; GFX90A-NEXT: v_mul_hi_u32 v6, v3, v5 +; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v8, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v5, v3, v5 ; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v7, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v6, v8, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v7, vcc -; GFX90A-NEXT: v_mul_lo_u32 v5, s0, v3 -; GFX90A-NEXT: v_mul_hi_u32 v7, s0, v2 -; GFX90A-NEXT: v_add_u32_e32 v5, v7, v5 -; GFX90A-NEXT: v_mul_lo_u32 v7, s1, v2 -; GFX90A-NEXT: v_add_u32_e32 v5, v5, v7 -; GFX90A-NEXT: v_mul_lo_u32 v8, s0, v2 -; GFX90A-NEXT: v_mul_hi_u32 v9, v3, v8 -; GFX90A-NEXT: v_mul_lo_u32 v10, v3, v8 -; GFX90A-NEXT: v_mul_lo_u32 v12, v2, v5 -; GFX90A-NEXT: v_mul_hi_u32 v8, v2, v8 -; GFX90A-NEXT: v_mul_hi_u32 v11, v2, v5 -; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v12 -; GFX90A-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v11, vcc -; GFX90A-NEXT: v_add_co_u32_e32 v8, vcc, v8, v10 -; GFX90A-NEXT: v_mul_hi_u32 v7, v3, v5 -; GFX90A-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v9, vcc -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v4, vcc -; GFX90A-NEXT: v_mul_lo_u32 v5, v3, v5 -; GFX90A-NEXT: v_add_co_u32_e32 v5, vcc, v8, v5 ; GFX90A-NEXT: s_ashr_i32 s10, s7, 31 -; GFX90A-NEXT: v_addc_co_u32_e32 v7, vcc, v6, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc ; GFX90A-NEXT: s_add_u32 s0, s6, s10 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v5 ; GFX90A-NEXT: s_mov_b32 s11, s10 ; GFX90A-NEXT: s_addc_u32 s1, s7, s10 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v7, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v6, vcc ; GFX90A-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] -; GFX90A-NEXT: v_mul_lo_u32 v7, s6, v3 -; GFX90A-NEXT: v_mul_hi_u32 v8, s6, v2 +; GFX90A-NEXT: v_mul_lo_u32 v6, s6, v3 +; GFX90A-NEXT: v_mul_hi_u32 v7, s6, v2 ; GFX90A-NEXT: v_mul_hi_u32 v5, s6, v3 -; GFX90A-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 +; GFX90A-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 ; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc -; GFX90A-NEXT: v_mul_hi_u32 v9, s7, v2 +; GFX90A-NEXT: v_mul_hi_u32 v8, s7, v2 ; GFX90A-NEXT: v_mul_lo_u32 v2, s7, v2 -; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v7, v2 -; GFX90A-NEXT: v_mul_hi_u32 v8, s7, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v9, vcc -; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v8, v4, vcc +; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v6, v2 +; GFX90A-NEXT: v_mul_hi_u32 v7, s7, v3 +; GFX90A-NEXT: v_addc_co_u32_e32 v2, vcc, v5, v8, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v5, vcc, v7, v4, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, s7, v3 ; GFX90A-NEXT: v_add_co_u32_e32 v2, vcc, v2, v3 -; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc +; GFX90A-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc ; GFX90A-NEXT: v_mul_lo_u32 v3, s4, v3 ; GFX90A-NEXT: v_mul_hi_u32 v5, s4, v2 ; GFX90A-NEXT: v_add_u32_e32 v3, v5, v3 diff --git a/llvm/test/CodeGen/AMDGPU/bypass-div.ll b/llvm/test/CodeGen/AMDGPU/bypass-div.ll index 51c0b76b91ec..ec225f1636a1 100644 --- a/llvm/test/CodeGen/AMDGPU/bypass-div.ll +++ b/llvm/test/CodeGen/AMDGPU/bypass-div.ll @@ -27,7 +27,6 @@ define i64 @sdiv64(i64 %a, i64 %b) { ; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v3, vcc ; GFX9-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GFX9-NEXT: v_rcp_f32_e32 v5, v5 -; GFX9-NEXT: v_mov_b32_e32 v15, 0 ; GFX9-NEXT: v_mov_b32_e32 v14, 0 ; GFX9-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GFX9-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 @@ -40,20 +39,20 @@ define i64 @sdiv64(i64 %a, i64 %b) { ; GFX9-NEXT: v_mul_hi_u32 v10, v7, v5 ; GFX9-NEXT: v_mul_lo_u32 v12, v7, v5 ; GFX9-NEXT: v_add3_u32 v9, v10, v11, v9 -; GFX9-NEXT: v_mul_lo_u32 v11, v5, v9 -; GFX9-NEXT: v_mul_hi_u32 v13, v5, v12 -; GFX9-NEXT: v_mul_hi_u32 v10, v5, v9 -; GFX9-NEXT: v_mul_hi_u32 v16, v6, v9 +; GFX9-NEXT: v_mul_lo_u32 v10, v5, v9 +; GFX9-NEXT: v_mul_hi_u32 v11, v5, v12 +; GFX9-NEXT: v_mul_hi_u32 v13, v5, v9 +; GFX9-NEXT: v_mul_hi_u32 v15, v6, v9 ; GFX9-NEXT: v_mul_lo_u32 v9, v6, v9 -; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v13, v11 +; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v13, vcc ; GFX9-NEXT: v_mul_lo_u32 v13, v6, v12 ; GFX9-NEXT: v_mul_hi_u32 v12, v6, v12 -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v10, vcc -; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v13 -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v10, v12, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v14, vcc +; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v10, v13 +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v11, v12, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v15, v14, vcc ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9 -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v11, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v10, vcc ; GFX9-NEXT: v_mul_lo_u32 v9, v7, v6 @@ -68,13 +67,13 @@ define i64 @sdiv64(i64 %a, i64 %b) { ; GFX9-NEXT: v_mul_lo_u32 v7, v6, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v6, v8 ; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11 -; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v15, v13, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v13, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v8 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v11, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v12, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v14, vcc ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v15, v9, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v8, vcc ; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v1 @@ -86,7 +85,7 @@ define i64 @sdiv64(i64 %a, i64 %b) { ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v7, vcc ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v15, v10, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_mul_lo_u32 v10, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v11, v1, v6 @@ -95,7 +94,7 @@ define i64 @sdiv64(i64 %a, i64 %b) { ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v14, vcc ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v15, v8, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v3, v5 ; GFX9-NEXT: v_mul_lo_u32 v9, v2, v6 ; GFX9-NEXT: v_mul_hi_u32 v10, v2, v5 @@ -188,7 +187,6 @@ define i64 @udiv64(i64 %a, i64 %b) { ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc ; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GFX9-NEXT: v_rcp_f32_e32 v4, v4 -; GFX9-NEXT: v_mov_b32_e32 v13, 0 ; GFX9-NEXT: v_mov_b32_e32 v12, 0 ; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 @@ -203,18 +201,18 @@ define i64 @udiv64(i64 %a, i64 %b) { ; GFX9-NEXT: v_add3_u32 v8, v10, v8, v9 ; GFX9-NEXT: v_mul_hi_u32 v9, v4, v11 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v8 -; GFX9-NEXT: v_mul_hi_u32 v14, v4, v8 -; GFX9-NEXT: v_mul_hi_u32 v15, v5, v8 +; GFX9-NEXT: v_mul_hi_u32 v13, v4, v8 +; GFX9-NEXT: v_mul_hi_u32 v14, v5, v8 ; GFX9-NEXT: v_mul_lo_u32 v8, v5, v8 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc -; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11 +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v13, vcc +; GFX9-NEXT: v_mul_lo_u32 v13, v5, v11 ; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11 -; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v14 +; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v13 ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v14, v12, vcc ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v9, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5 @@ -224,18 +222,18 @@ define i64 @udiv64(i64 %a, i64 %b) { ; GFX9-NEXT: v_add3_u32 v7, v9, v8, v7 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v14, v4, v7 +; GFX9-NEXT: v_mul_hi_u32 v13, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v6 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 ; GFX9-NEXT: v_mul_hi_u32 v8, v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v13, v14, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v13, vcc ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v11, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v12, vcc ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5 @@ -244,14 +242,14 @@ define i64 @udiv64(i64 %a, i64 %b) { ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v8 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v12, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v13, v6, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc ; GFX9-NEXT: v_mul_lo_u32 v6, v3, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v2, v5 ; GFX9-NEXT: v_mul_hi_u32 v8, v2, v4 @@ -344,7 +342,6 @@ define i64 @srem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc ; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GFX9-NEXT: v_rcp_f32_e32 v4, v4 -; GFX9-NEXT: v_mov_b32_e32 v14, 0 ; GFX9-NEXT: v_mov_b32_e32 v13, 0 ; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 @@ -357,20 +354,20 @@ define i64 @srem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_mul_hi_u32 v9, v6, v4 ; GFX9-NEXT: v_mul_lo_u32 v11, v6, v4 ; GFX9-NEXT: v_add3_u32 v8, v9, v10, v8 -; GFX9-NEXT: v_mul_lo_u32 v10, v4, v8 -; GFX9-NEXT: v_mul_hi_u32 v12, v4, v11 -; GFX9-NEXT: v_mul_hi_u32 v9, v4, v8 -; GFX9-NEXT: v_mul_hi_u32 v15, v5, v8 +; GFX9-NEXT: v_mul_lo_u32 v9, v4, v8 +; GFX9-NEXT: v_mul_hi_u32 v10, v4, v11 +; GFX9-NEXT: v_mul_hi_u32 v12, v4, v8 +; GFX9-NEXT: v_mul_hi_u32 v14, v5, v8 ; GFX9-NEXT: v_mul_lo_u32 v8, v5, v8 -; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v12, v10 +; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9 +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v12, vcc ; GFX9-NEXT: v_mul_lo_u32 v12, v5, v11 ; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v14, v9, vcc -; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v10, v12 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v11, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v13, vcc +; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v12 +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v14, v13, vcc ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v14, v10, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v9, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5 @@ -385,13 +382,13 @@ define i64 @srem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 ; GFX9-NEXT: v_mul_hi_u32 v8, v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v14, v12, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v12, vcc ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v11, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v13, vcc ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v14, v8, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc ; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v1 @@ -403,7 +400,7 @@ define i64 @srem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v6, vcc ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v6 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v8, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v14, v9, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc ; GFX9-NEXT: v_mul_lo_u32 v9, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v10, v1, v5 @@ -412,7 +409,7 @@ define i64 @srem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v10, v13, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v14, v7, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v7, vcc ; GFX9-NEXT: v_mul_lo_u32 v7, v3, v4 ; GFX9-NEXT: v_mul_lo_u32 v5, v2, v5 ; GFX9-NEXT: v_mul_hi_u32 v8, v2, v4 @@ -501,7 +498,6 @@ define i64 @urem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc ; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GFX9-NEXT: v_rcp_f32_e32 v4, v4 -; GFX9-NEXT: v_mov_b32_e32 v13, 0 ; GFX9-NEXT: v_mov_b32_e32 v12, 0 ; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 @@ -516,18 +512,18 @@ define i64 @urem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_add3_u32 v8, v10, v8, v9 ; GFX9-NEXT: v_mul_hi_u32 v9, v4, v11 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v8 -; GFX9-NEXT: v_mul_hi_u32 v14, v4, v8 -; GFX9-NEXT: v_mul_hi_u32 v15, v5, v8 +; GFX9-NEXT: v_mul_hi_u32 v13, v4, v8 +; GFX9-NEXT: v_mul_hi_u32 v14, v5, v8 ; GFX9-NEXT: v_mul_lo_u32 v8, v5, v8 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc -; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11 +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v13, vcc +; GFX9-NEXT: v_mul_lo_u32 v13, v5, v11 ; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11 -; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v14 +; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v13 ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v14, v12, vcc ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v9, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5 @@ -537,18 +533,18 @@ define i64 @urem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_add3_u32 v7, v9, v8, v7 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v14, v4, v7 +; GFX9-NEXT: v_mul_hi_u32 v13, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v6 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 ; GFX9-NEXT: v_mul_hi_u32 v8, v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v13, v14, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v13, vcc ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v11, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v12, vcc ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5 @@ -557,14 +553,14 @@ define i64 @urem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v8 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v12, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v13, v6, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc ; GFX9-NEXT: v_mul_lo_u32 v6, v3, v4 ; GFX9-NEXT: v_mul_lo_u32 v5, v2, v5 ; GFX9-NEXT: v_mul_hi_u32 v7, v2, v4 @@ -780,7 +776,6 @@ define <2 x i64> @sdivrem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_subb_co_u32_e32 v8, vcc, 0, v3, vcc ; GFX9-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GFX9-NEXT: v_rcp_f32_e32 v5, v5 -; GFX9-NEXT: v_mov_b32_e32 v15, 0 ; GFX9-NEXT: v_mov_b32_e32 v14, 0 ; GFX9-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GFX9-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 @@ -793,20 +788,20 @@ define <2 x i64> @sdivrem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_mul_hi_u32 v10, v7, v5 ; GFX9-NEXT: v_mul_lo_u32 v12, v7, v5 ; GFX9-NEXT: v_add3_u32 v9, v10, v11, v9 -; GFX9-NEXT: v_mul_lo_u32 v11, v5, v9 -; GFX9-NEXT: v_mul_hi_u32 v13, v5, v12 -; GFX9-NEXT: v_mul_hi_u32 v10, v5, v9 -; GFX9-NEXT: v_mul_hi_u32 v16, v6, v9 +; GFX9-NEXT: v_mul_lo_u32 v10, v5, v9 +; GFX9-NEXT: v_mul_hi_u32 v11, v5, v12 +; GFX9-NEXT: v_mul_hi_u32 v13, v5, v9 +; GFX9-NEXT: v_mul_hi_u32 v15, v6, v9 ; GFX9-NEXT: v_mul_lo_u32 v9, v6, v9 -; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v13, v11 +; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v13, vcc ; GFX9-NEXT: v_mul_lo_u32 v13, v6, v12 ; GFX9-NEXT: v_mul_hi_u32 v12, v6, v12 -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v10, vcc -; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v11, v13 -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v10, v12, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v16, v14, vcc +; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v10, v13 +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v11, v12, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v15, v14, vcc ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v10, v9 -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v11, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v11, vcc ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v9 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v10, vcc ; GFX9-NEXT: v_mul_lo_u32 v9, v7, v6 @@ -821,13 +816,13 @@ define <2 x i64> @sdivrem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_mul_lo_u32 v7, v6, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v6, v8 ; GFX9-NEXT: v_add_co_u32_e32 v11, vcc, v12, v11 -; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, v15, v13, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v13, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v8 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v11, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v12, v10, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v9, v14, vcc ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v15, v9, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v7 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v6, v8, vcc ; GFX9-NEXT: v_ashrrev_i32_e32 v7, 31, v1 @@ -839,7 +834,7 @@ define <2 x i64> @sdivrem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v7, vcc ; GFX9-NEXT: v_xor_b32_e32 v1, v1, v7 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v15, v10, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_mul_lo_u32 v10, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v5, v1, v5 ; GFX9-NEXT: v_mul_hi_u32 v11, v1, v6 @@ -848,7 +843,7 @@ define <2 x i64> @sdivrem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v9, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v11, v14, vcc ; GFX9-NEXT: v_add_co_u32_e32 v5, vcc, v5, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v15, v8, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v8, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v3, v5 ; GFX9-NEXT: v_mul_lo_u32 v9, v2, v6 ; GFX9-NEXT: v_mul_hi_u32 v10, v2, v5 @@ -961,7 +956,6 @@ define <2 x i64> @udivrem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, 0, v3, vcc ; GFX9-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GFX9-NEXT: v_rcp_f32_e32 v4, v4 -; GFX9-NEXT: v_mov_b32_e32 v13, 0 ; GFX9-NEXT: v_mov_b32_e32 v12, 0 ; GFX9-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GFX9-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 @@ -976,18 +970,18 @@ define <2 x i64> @udivrem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_add3_u32 v8, v10, v8, v9 ; GFX9-NEXT: v_mul_hi_u32 v9, v4, v11 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v8 -; GFX9-NEXT: v_mul_hi_u32 v14, v4, v8 -; GFX9-NEXT: v_mul_hi_u32 v15, v5, v8 +; GFX9-NEXT: v_mul_hi_u32 v13, v4, v8 +; GFX9-NEXT: v_mul_hi_u32 v14, v5, v8 ; GFX9-NEXT: v_mul_lo_u32 v8, v5, v8 ; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v13, v14, vcc -; GFX9-NEXT: v_mul_lo_u32 v14, v5, v11 +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, 0, v13, vcc +; GFX9-NEXT: v_mul_lo_u32 v13, v5, v11 ; GFX9-NEXT: v_mul_hi_u32 v11, v5, v11 -; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v14 +; GFX9-NEXT: v_add_co_u32_e32 v9, vcc, v9, v13 ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v10, v11, vcc -; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v15, v12, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v14, v12, vcc ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v9, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v13, v10, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v9, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v6, v5 @@ -997,18 +991,18 @@ define <2 x i64> @udivrem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_add3_u32 v7, v9, v8, v7 ; GFX9-NEXT: v_mul_lo_u32 v10, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v11, v4, v6 -; GFX9-NEXT: v_mul_hi_u32 v14, v4, v7 +; GFX9-NEXT: v_mul_hi_u32 v13, v4, v7 ; GFX9-NEXT: v_mul_hi_u32 v9, v5, v6 ; GFX9-NEXT: v_mul_lo_u32 v6, v5, v6 ; GFX9-NEXT: v_mul_hi_u32 v8, v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v11, v10 -; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v13, v14, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v13, vcc ; GFX9-NEXT: v_mul_lo_u32 v7, v5, v7 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v10, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v11, v9, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v8, v12, vcc ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v7 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v6 ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v7, vcc ; GFX9-NEXT: v_mul_lo_u32 v6, v0, v5 @@ -1017,14 +1011,14 @@ define <2 x i64> @udivrem64(i64 %a, i64 %b) { ; GFX9-NEXT: v_mul_hi_u32 v9, v1, v5 ; GFX9-NEXT: v_mul_lo_u32 v5, v1, v5 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v7, v6 -; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v13, v8, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v8, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v4 ; GFX9-NEXT: v_mul_hi_u32 v4, v1, v4 ; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, v6, v8 ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, v9, v12, vcc ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v5 -; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v13, v6, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v6, vcc ; GFX9-NEXT: v_mul_lo_u32 v6, v3, v4 ; GFX9-NEXT: v_mul_lo_u32 v7, v2, v5 ; GFX9-NEXT: v_mul_hi_u32 v8, v2, v4 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll index fafbb4c54142..40ece5345391 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.mulo.ll @@ -89,7 +89,6 @@ define { i64, i1 } @smulo_i64_s_s(i64 %x, i64 %y) { ; SI-NEXT: v_mul_hi_u32 v9, v0, v2 ; SI-NEXT: v_mul_hi_i32 v10, v1, v3 ; SI-NEXT: v_mul_lo_u32 v11, v1, v3 -; SI-NEXT: v_mov_b32_e32 v12, 0 ; SI-NEXT: v_mul_lo_u32 v4, v0, v2 ; SI-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc @@ -100,14 +99,14 @@ define { i64, i1 } @smulo_i64_s_s(i64 %x, i64 %y) { ; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; SI-NEXT: v_mov_b32_e32 v7, v6 ; SI-NEXT: v_add_i32_e32 v8, vcc, v8, v11 -; SI-NEXT: v_addc_u32_e32 v9, vcc, v12, v9, vcc +; SI-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc ; SI-NEXT: v_sub_i32_e32 v2, vcc, v8, v2 -; SI-NEXT: v_subb_u32_e32 v10, vcc, v9, v12, vcc +; SI-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v9, vcc ; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1 ; SI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc ; SI-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc ; SI-NEXT: v_sub_i32_e32 v0, vcc, v2, v0 -; SI-NEXT: v_subb_u32_e32 v8, vcc, v1, v12, vcc +; SI-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc ; SI-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3 ; SI-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc @@ -132,16 +131,15 @@ define { i64, i1 } @smulo_i64_s_s(i64 %x, i64 %y) { ; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, v8, v4, vcc ; GFX9-NEXT: v_mul_lo_u32 v8, v1, v3 ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v10, vcc -; GFX9-NEXT: v_mov_b32_e32 v10, 0 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v4, v8 -; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v10, v9, vcc +; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc ; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, v4, v2 -; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v8, v10, vcc +; GFX9-NEXT: v_subbrev_co_u32_e32 v10, vcc, 0, v8, vcc ; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v11, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v10, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v8, v4, v9, vcc ; GFX9-NEXT: v_sub_co_u32_e32 v9, vcc, v8, v0 -; GFX9-NEXT: v_subb_co_u32_e32 v4, vcc, v1, v10, vcc +; GFX9-NEXT: v_subbrev_co_u32_e32 v4, vcc, 0, v1, vcc ; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, 0, v3 ; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v4, vcc ; GFX9-NEXT: v_add3_u32 v1, v6, v5, v7 @@ -296,46 +294,45 @@ define amdgpu_kernel void @smulo_i64_s(i64 %x, i64 %y) { ; SI-LABEL: smulo_i64_s: ; SI: ; %bb.0: ; %bb ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; SI-NEXT: v_mov_b32_e32 v0, 0 ; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: v_mov_b32_e32 v1, s2 -; SI-NEXT: v_mul_hi_u32 v2, s1, v1 +; SI-NEXT: v_mov_b32_e32 v0, s2 +; SI-NEXT: v_mul_hi_u32 v1, s1, v0 ; SI-NEXT: s_mul_i32 s4, s1, s2 -; SI-NEXT: v_mov_b32_e32 v3, s3 -; SI-NEXT: v_mul_hi_u32 v4, s0, v3 +; SI-NEXT: v_mov_b32_e32 v2, s3 +; SI-NEXT: v_mul_hi_u32 v3, s0, v2 ; SI-NEXT: s_mul_i32 s5, s0, s3 -; SI-NEXT: v_mul_hi_u32 v1, s0, v1 -; SI-NEXT: v_mul_hi_i32 v3, s1, v3 +; SI-NEXT: v_mul_hi_u32 v0, s0, v0 +; SI-NEXT: v_mul_hi_i32 v2, s1, v2 ; SI-NEXT: s_mul_i32 s6, s1, s3 ; SI-NEXT: s_cmp_lt_i32 s1, 0 ; SI-NEXT: s_mul_i32 s1, s0, s2 -; SI-NEXT: v_add_i32_e32 v5, vcc, s5, v1 -; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; SI-NEXT: v_mov_b32_e32 v6, s1 -; SI-NEXT: v_add_i32_e32 v5, vcc, s4, v5 -; SI-NEXT: v_addc_u32_e32 v2, vcc, v4, v2, vcc +; SI-NEXT: v_add_i32_e32 v4, vcc, s5, v0 ; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; SI-NEXT: v_add_i32_e32 v1, vcc, s5, v1 -; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2 -; SI-NEXT: v_addc_u32_e32 v3, vcc, v0, v3, vcc -; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v1 -; SI-NEXT: v_subrev_i32_e32 v1, vcc, s2, v2 -; SI-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v3, vcc +; SI-NEXT: v_mov_b32_e32 v5, s1 +; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v4 +; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc +; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; SI-NEXT: v_add_i32_e32 v0, vcc, s5, v0 +; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1 +; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; SI-NEXT: v_add_i32_e32 v4, vcc, s4, v0 +; SI-NEXT: v_subrev_i32_e32 v3, vcc, s2, v1 +; SI-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v2, vcc ; SI-NEXT: s_cselect_b64 vcc, -1, 0 ; SI-NEXT: s_cmp_lt_i32 s3, 0 ; SI-NEXT: v_ashrrev_i32_e32 v0, 31, v4 -; SI-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc -; SI-NEXT: v_cndmask_b32_e32 v2, v2, v1, vcc +; SI-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc +; SI-NEXT: v_cndmask_b32_e32 v6, v1, v3, vcc ; SI-NEXT: v_mov_b32_e32 v1, v0 -; SI-NEXT: v_subrev_i32_e32 v5, vcc, s0, v2 -; SI-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v3, vcc +; SI-NEXT: v_subrev_i32_e32 v7, vcc, s0, v6 +; SI-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v2, vcc ; SI-NEXT: s_cselect_b64 vcc, -1, 0 -; SI-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; SI-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc +; SI-NEXT: v_cndmask_b32_e32 v3, v2, v3, vcc +; SI-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc ; SI-NEXT: v_cmp_ne_u64_e32 vcc, v[2:3], v[0:1] ; SI-NEXT: v_cndmask_b32_e64 v1, v4, 0, vcc -; SI-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc +; SI-NEXT: v_cndmask_b32_e64 v0, v5, 0, vcc ; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; SI-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll b/llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll index eaa45b929b2b..769a236abce6 100644 --- a/llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll +++ b/llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll @@ -138,17 +138,16 @@ define amdgpu_kernel void @test_umul24_i16_vgpr_sext(i32 addrspace(1)* %out, i16 ; VI: ; %bb.0: ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; VI-NEXT: v_mov_b32_e32 v4, 0 ; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: v_mov_b32_e32 v3, s7 ; VI-NEXT: v_add_u32_e32 v2, vcc, s6, v0 -; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc +; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v1 ; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0 -; VI-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc +; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: flat_load_ushort v2, v[2:3] ; VI-NEXT: flat_load_ushort v0, v[0:1] ; VI-NEXT: s_mov_b32 s0, s4 diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll index dc03778da7ac..5962502bfffe 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -6,7 +6,6 @@ define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_sdiv: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd -; GCN-NEXT: v_mov_b32_e32 v7, 0 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) @@ -43,41 +42,41 @@ define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc -; GCN-NEXT: v_mul_lo_u32 v8, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v5 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 -; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13] -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; GCN-NEXT: v_mul_hi_u32 v8, v2, v3 +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v1, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc ; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 ; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s5, v0 +; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13] ; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s4, v0 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v3 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v6, vcc +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc ; GCN-NEXT: v_mul_lo_u32 v3, s2, v2 @@ -86,7 +85,7 @@ define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-NEXT: v_mul_hi_u32 v6, s3, v2 ; GCN-NEXT: v_mul_lo_u32 v2, s3, v2 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GCN-NEXT: v_mul_lo_u32 v5, s3, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 ; GCN-NEXT: s_mov_b32 s4, s0 @@ -94,7 +93,7 @@ define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 ; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s11, v0 @@ -262,7 +261,6 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) { ; GCN-NEXT: v_subb_u32_e32 v8, vcc, 0, v3, vcc ; GCN-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6 ; GCN-NEXT: v_rcp_f32_e32 v5, v5 -; GCN-NEXT: v_mov_b32_e32 v15, 0 ; GCN-NEXT: v_mov_b32_e32 v14, 0 ; GCN-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GCN-NEXT: v_mul_f32_e32 v6, 0x2f800000, v5 @@ -276,20 +274,20 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) { ; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; GCN-NEXT: v_mul_lo_u32 v10, v7, v5 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v11 -; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 -; GCN-NEXT: v_mul_hi_u32 v13, v5, v10 -; GCN-NEXT: v_mul_hi_u32 v11, v5, v9 -; GCN-NEXT: v_mul_hi_u32 v16, v6, v9 +; GCN-NEXT: v_mul_lo_u32 v11, v5, v9 +; GCN-NEXT: v_mul_hi_u32 v12, v5, v10 +; GCN-NEXT: v_mul_hi_u32 v13, v5, v9 +; GCN-NEXT: v_mul_hi_u32 v15, v6, v9 ; GCN-NEXT: v_mul_lo_u32 v9, v6, v9 -; GCN-NEXT: v_add_i32_e32 v12, vcc, v13, v12 +; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v13, vcc ; GCN-NEXT: v_mul_lo_u32 v13, v6, v10 ; GCN-NEXT: v_mul_hi_u32 v10, v6, v10 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v11, vcc -; GCN-NEXT: v_add_i32_e32 v12, vcc, v12, v13 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v11, v10, vcc -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v16, v14, vcc +; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v13 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v12, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v11, vcc, v15, v14, vcc ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v9, v7, v6 @@ -305,13 +303,13 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) { ; GCN-NEXT: v_mul_lo_u32 v7, v6, v7 ; GCN-NEXT: v_mul_hi_u32 v9, v6, v8 ; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 -; GCN-NEXT: v_addc_u32_e32 v12, vcc, v15, v13, vcc +; GCN-NEXT: v_addc_u32_e32 v12, vcc, 0, v13, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v6, v8 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7 ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v10, vcc ; GCN-NEXT: v_addc_u32_e32 v9, vcc, v9, v14, vcc ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v15, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc ; GCN-NEXT: v_ashrrev_i32_e32 v7, 31, v1 @@ -323,7 +321,7 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) { ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc ; GCN-NEXT: v_xor_b32_e32 v1, v1, v7 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v15, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v10, v1, v5 ; GCN-NEXT: v_mul_hi_u32 v5, v1, v5 ; GCN-NEXT: v_mul_hi_u32 v11, v1, v6 @@ -332,7 +330,7 @@ define i64 @v_test_sdiv(i64 %x, i64 %y) { ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v11, v14, vcc ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v2, v6 ; GCN-NEXT: v_mul_hi_u32 v9, v2, v5 ; GCN-NEXT: v_mul_lo_u32 v10, v3, v5 @@ -1113,7 +1111,6 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-LABEL: s_test_sdiv_k_num_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) @@ -1130,95 +1127,95 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s4, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v7, s5, v0 -; GCN-NEXT: v_mul_lo_u32 v6, s4, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 -; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s4, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s5, v0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_mul_lo_u32 v5, s4, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v4 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v7, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s5, v0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s4, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v3 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v5, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc -; GCN-NEXT: v_mul_lo_u32 v3, v1, 24 +; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 -; GCN-NEXT: v_mov_b32_e32 v5, s3 +; GCN-NEXT: v_mov_b32_e32 v4, s3 ; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc ; GCN-NEXT: v_mul_lo_u32 v1, s3, v0 -; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; GCN-NEXT: v_mul_lo_u32 v3, s2, v0 -; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v1 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v3 -; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc -; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3 -; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5 +; GCN-NEXT: v_mul_hi_u32 v2, s2, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_mul_lo_u32 v2, s2, v0 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, 24, v2 +; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc +; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v2 +; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v3 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] -; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 -; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1] -; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1] +; GCN-NEXT: v_add_i32_e64 v4, s[0:1], 2, v0 +; GCN-NEXT: v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1] +; GCN-NEXT: v_add_i32_e64 v6, s[0:1], 1, v0 +; GCN-NEXT: v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1] ; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 -; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc -; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v2, v6, v4, s[0:1] ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc ; GCN-NEXT: v_xor_b32_e32 v0, s8, v0 ; GCN-NEXT: v_xor_b32_e32 v1, s8, v1 ; GCN-NEXT: v_mov_b32_e32 v2, s8 @@ -1331,7 +1328,6 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) { ; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v1, vcc ; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 ; GCN-NEXT: v_rcp_f32_e32 v3, v3 -; GCN-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 ; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 @@ -1345,20 +1341,20 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) { ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v3 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9 -; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v3, v7 -; GCN-NEXT: v_mul_hi_u32 v14, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v9, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v8 +; GCN-NEXT: v_mul_hi_u32 v11, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v13, v4, v7 ; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc ; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 ; GCN-NEXT: v_mul_hi_u32 v8, v4, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v9, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v9, v8, vcc -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v12, vcc +; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v11 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v12, vcc ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc ; GCN-NEXT: v_mul_lo_u32 v7, v5, v4 @@ -1374,20 +1370,20 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) { ; GCN-NEXT: v_mul_lo_u32 v5, v4, v5 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v6 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v13, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v4, v6 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v12, vcc ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc ; GCN-NEXT: v_mul_lo_u32 v5, v4, 24 ; GCN-NEXT: v_mul_hi_u32 v3, v3, 24 ; GCN-NEXT: v_mul_hi_u32 v4, v4, 24 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v13, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v1, v3 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v3 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 @@ -1404,9 +1400,9 @@ define i64 @v_test_sdiv_k_num_i64(i64 %x) { ; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v1 ; GCN-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[4:5] ; GCN-NEXT: v_add_i32_e64 v7, s[4:5], 2, v3 -; GCN-NEXT: v_addc_u32_e64 v8, s[4:5], 0, v13, s[4:5] +; GCN-NEXT: v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5] ; GCN-NEXT: v_add_i32_e64 v9, s[4:5], 1, v3 -; GCN-NEXT: v_addc_u32_e64 v10, s[4:5], 0, v13, s[4:5] +; GCN-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5] ; GCN-NEXT: v_subb_u32_e32 v4, vcc, 0, v4, vcc ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v1 @@ -1533,7 +1529,6 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v1, vcc ; GCN-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4 ; GCN-NEXT: v_rcp_f32_e32 v3, v3 -; GCN-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: s_mov_b32 s4, 0x8000 ; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 @@ -1548,20 +1543,20 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v3 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v9 -; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v8 -; GCN-NEXT: v_mul_hi_u32 v9, v3, v7 -; GCN-NEXT: v_mul_hi_u32 v14, v4, v7 +; GCN-NEXT: v_mul_lo_u32 v9, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v8 +; GCN-NEXT: v_mul_hi_u32 v11, v3, v7 +; GCN-NEXT: v_mul_hi_u32 v13, v4, v7 ; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 -; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc ; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 ; GCN-NEXT: v_mul_hi_u32 v8, v4, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v9, vcc -; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v11 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v9, v8, vcc -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v12, vcc +; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v11 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v13, v12, vcc ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v8, vcc ; GCN-NEXT: v_mul_lo_u32 v7, v5, v4 @@ -1577,20 +1572,20 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_mul_lo_u32 v5, v4, v5 ; GCN-NEXT: v_mul_hi_u32 v7, v4, v6 ; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v13, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v4, v6 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v12, vcc ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc ; GCN-NEXT: v_lshrrev_b32_e32 v5, 17, v4 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 15, v4 ; GCN-NEXT: v_lshrrev_b32_e32 v3, 17, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v13, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v1, v3 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v3 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 @@ -1607,9 +1602,9 @@ define i64 @v_test_sdiv_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v6, v1 ; GCN-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[4:5] ; GCN-NEXT: v_add_i32_e64 v7, s[4:5], 2, v3 -; GCN-NEXT: v_addc_u32_e64 v8, s[4:5], 0, v13, s[4:5] +; GCN-NEXT: v_addc_u32_e64 v8, s[4:5], 0, 0, s[4:5] ; GCN-NEXT: v_add_i32_e64 v9, s[4:5], 1, v3 -; GCN-NEXT: v_addc_u32_e64 v10, s[4:5], 0, v13, s[4:5] +; GCN-NEXT: v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5] ; GCN-NEXT: v_subb_u32_e32 v4, vcc, 0, v4, vcc ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v1 @@ -1797,11 +1792,10 @@ define i64 @v_test_sdiv_pow2_k_den_i64(i64 %x) { ; GCN-IR-NEXT: v_and_b32_e32 v9, 0x8000, v9 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8] ; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 -; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 -; GCN-IR-NEXT: v_subb_u32_e64 v10, s[4:5], v10, v13, s[4:5] +; GCN-IR-NEXT: v_subbrev_u32_e64 v10, s[4:5], 0, v10, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] diff --git a/llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir b/llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir index 27a3f98dd128..7453a70c46dc 100644 --- a/llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir +++ b/llvm/test/CodeGen/AMDGPU/set-gpr-idx-peephole.mir @@ -8,14 +8,14 @@ body: | ; GCN-LABEL: name: simple ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -26,16 +26,16 @@ body: | ; GCN-LABEL: name: salu_in_between ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: $sgpr0 = S_MOV_B32 $sgpr2 - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode $sgpr0 = S_MOV_B32 $sgpr2 S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -46,18 +46,18 @@ body: | ; GCN-LABEL: name: valu_write_in_between ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode - ; GCN: $vgpr20 = V_MOV_B32_e32 1, implicit $exec + ; GCN: $vgpr20 = V_MOV_B32_indirect_read 1, implicit $exec ; GCN: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode - $vgpr20 = V_MOV_B32_e32 1, implicit $exec + $vgpr20 = V_MOV_B32_indirect_read 1, implicit $exec S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -68,18 +68,18 @@ body: | ; GCN-LABEL: name: valu_read_in_between ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: V_NOP_e32 implicit $exec, implicit $vgpr0 ; GCN: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode V_NOP_e32 implicit $exec, implicit $vgpr0 S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -90,18 +90,18 @@ body: | ; GCN-LABEL: name: changed_index ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: $sgpr2 = S_MOV_B32 1 ; GCN: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode $sgpr2 = S_MOV_B32 1 S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -112,18 +112,18 @@ body: | ; GCN-LABEL: name: implicitly_changed_index ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: S_NOP 0, implicit-def $sgpr2 ; GCN: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_NOP 0, implicit-def $sgpr2 S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -134,18 +134,18 @@ body: | ; GCN-LABEL: name: changed_m0 ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: $m0 = S_MOV_B32 1 ; GCN: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode $m0 = S_MOV_B32 1 S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -156,18 +156,18 @@ body: | ; GCN-LABEL: name: implicitly_changed_m0 ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: S_NOP 0, implicit-def $m0 ; GCN: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_NOP 0, implicit-def $m0 S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -178,14 +178,14 @@ body: | ; GCN-LABEL: name: same_imm_index ; GCN: S_SET_GPR_IDX_ON 1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON 1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON 1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -196,16 +196,16 @@ body: | ; GCN-LABEL: name: different_imm_index ; GCN: S_SET_GPR_IDX_ON 1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: S_SET_GPR_IDX_ON 2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON 1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON 2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -216,16 +216,16 @@ body: | ; GCN-LABEL: name: different_gpr_index ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: S_SET_GPR_IDX_ON killed $sgpr1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON killed $sgpr1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -236,22 +236,22 @@ body: | ; GCN-LABEL: name: different_gpr_index_then_same_index ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: S_SET_GPR_IDX_ON $sgpr1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -263,15 +263,15 @@ body: | ; GCN-LABEL: name: use_m0_with_idx_off ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -282,18 +282,18 @@ body: | ; GCN-LABEL: name: three_in_a_row ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 - ; GCN: $vgpr17 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 - ; GCN: $vgpr18 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr17 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr18 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr17 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr17 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr18 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr18 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -304,20 +304,20 @@ body: | ; GCN-LABEL: name: different_gpr_index_then_two_same_indexes ; GCN: S_SET_GPR_IDX_ON $sgpr1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -328,20 +328,20 @@ body: | ; GCN-LABEL: name: two_same_indexes_then_different ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: S_SET_GPR_IDX_ON killed $sgpr1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON killed $sgpr1, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -352,16 +352,16 @@ body: | ; GCN-LABEL: name: indirect_mov ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 - ; GCN: V_MOV_B32_indirect undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3) - ; GCN: V_MOV_B32_indirect undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3) + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: V_MOV_B32_indirect_write undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3) + ; GCN: V_MOV_B32_indirect_write undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3) ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 - V_MOV_B32_indirect undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3) + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + V_MOV_B32_indirect_write undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3) S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $m0, implicit-def $mode, implicit undef $m0, implicit $mode - V_MOV_B32_indirect undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3) + V_MOV_B32_indirect_write undef $vgpr0, undef $vgpr3, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 3) S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ... @@ -372,20 +372,20 @@ body: | ; GCN-LABEL: name: simple_bundle ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: } ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: } BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode } BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode } ... @@ -397,22 +397,22 @@ body: | ; GCN-LABEL: name: salu_in_between_bundle ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: } ; GCN: $sgpr0 = S_MOV_B32 $sgpr2 ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: } BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode } $sgpr0 = S_MOV_B32 $sgpr2 BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode } ... @@ -424,24 +424,24 @@ body: | ; GCN-LABEL: name: valu_in_between_bundle ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: } - ; GCN: $vgpr20 = V_MOV_B32_e32 1, implicit $exec + ; GCN: $vgpr20 = V_MOV_B32_indirect_read 1, implicit $exec ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { ; GCN: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: } BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode } - $vgpr20 = V_MOV_B32_e32 1, implicit $exec + $vgpr20 = V_MOV_B32_indirect_read 1, implicit $exec BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode } ... @@ -453,24 +453,24 @@ body: | ; GCN-LABEL: name: changed_index_bundle ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: } ; GCN: $sgpr2 = S_MOV_B32 1 ; GCN: BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { ; GCN: S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: } BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode } $sgpr2 = S_MOV_B32 1 BUNDLE implicit-def $m0, implicit-def $m0_lo16, implicit-def $m0_hi16, implicit-def $mode, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit $sgpr2, implicit $m0, implicit $mode, implicit undef $vgpr0, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 { S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode } ... @@ -482,17 +482,17 @@ body: | ; GCN: bb.0: ; GCN: successors: %bb.1(0x80000000) ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: S_CBRANCH_VCCZ %bb.1, implicit $vcc ; GCN: bb.1: bb.0: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_CBRANCH_VCCZ %bb.1, implicit $vcc bb.1: @@ -505,16 +505,16 @@ body: | ; GCN: bb.0: ; GCN: successors: ; GCN: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - ; GCN: $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 - ; GCN: $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + ; GCN: $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 ; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode ; GCN: bb.1: bb.0: S_SET_GPR_IDX_ON $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr16 = V_MOV_B32_e32 undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_SET_GPR_IDX_ON killed $sgpr2, 1, implicit-def $mode, implicit-def $m0, implicit $mode, implicit undef $m0 - $vgpr15 = V_MOV_B32_e32 undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 + $vgpr15 = V_MOV_B32_indirect_read undef $vgpr0, implicit $exec, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0 S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode S_CBRANCH_EXECZ %bb.1, implicit $exec bb.1: diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll index e70184481b05..096f7c0a8c7e 100644 --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -7,7 +7,6 @@ define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 -; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) @@ -21,69 +20,69 @@ define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) { ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_mov_b32 s5, s9 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s0, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s0, v0 -; GCN-NEXT: v_mul_lo_u32 v7, s1, v0 -; GCN-NEXT: v_mul_lo_u32 v6, s0, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 -; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc -; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s0, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s0, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s0, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s0, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s1, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_mul_lo_u32 v5, s0, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v4 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s10, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 -; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 -; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 -; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s0, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s0, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s1, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s0, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v3 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s10, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v2 +; GCN-NEXT: v_mul_hi_u32 v6, s11, v2 +; GCN-NEXT: v_mul_lo_u32 v2, s11, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 ; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 @@ -239,7 +238,6 @@ define i64 @v_test_srem(i64 %x, i64 %y) { ; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc ; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GCN-NEXT: v_rcp_f32_e32 v4, v4 -; GCN-NEXT: v_mov_b32_e32 v14, 0 ; GCN-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 @@ -253,20 +251,20 @@ define i64 @v_test_srem(i64 %x, i64 %y) { ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; GCN-NEXT: v_mul_lo_u32 v9, v6, v4 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 -; GCN-NEXT: v_mul_hi_u32 v12, v4, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v4, v8 -; GCN-NEXT: v_mul_hi_u32 v15, v5, v8 +; GCN-NEXT: v_mul_lo_u32 v10, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v11, v4, v9 +; GCN-NEXT: v_mul_hi_u32 v12, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v14, v5, v8 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc ; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 ; GCN-NEXT: v_mul_hi_u32 v9, v5, v9 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc +; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v12 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v13, vcc ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v6, v5 @@ -282,13 +280,13 @@ define i64 @v_test_srem(i64 %x, i64 %y) { ; GCN-NEXT: v_mul_lo_u32 v6, v5, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v5, v7 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v14, v12, vcc +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc ; GCN-NEXT: v_mul_lo_u32 v7, v5, v7 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc ; GCN-NEXT: v_ashrrev_i32_e32 v6, 31, v1 @@ -300,7 +298,7 @@ define i64 @v_test_srem(i64 %x, i64 %y) { ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v6, vcc ; GCN-NEXT: v_xor_b32_e32 v1, v1, v6 ; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v14, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc ; GCN-NEXT: v_mul_lo_u32 v9, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v10, v1, v5 @@ -309,7 +307,7 @@ define i64 @v_test_srem(i64 %x, i64 %y) { ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v7, vcc, v10, v13, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc ; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 ; GCN-NEXT: v_mul_hi_u32 v7, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v4 @@ -872,7 +870,7 @@ define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd -; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v6, 0 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) @@ -890,77 +888,76 @@ define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 ; GCN-NEXT: s_ashr_i32 s10, s11, 31 ; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 -; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_mov_b32 s11, s10 ; GCN-NEXT: s_mov_b32 s4, s8 -; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: s_mov_b32 s5, s9 -; GCN-NEXT: v_mul_lo_u32 v3, s0, v2 -; GCN-NEXT: v_mul_hi_u32 v4, s0, v0 -; GCN-NEXT: v_mul_lo_u32 v6, s1, v0 -; GCN-NEXT: v_mul_lo_u32 v5, s0, v0 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 -; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v7, v8, vcc -; GCN-NEXT: v_mul_lo_u32 v8, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc -; GCN-NEXT: v_mul_lo_u32 v3, s0, v2 -; GCN-NEXT: v_mul_hi_u32 v4, s0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 ; GCN-NEXT: v_mul_lo_u32 v5, s1, v0 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v0 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 -; GCN-NEXT: v_mul_hi_u32 v5, v2, v3 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v7, v10, vcc -; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc -; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc -; GCN-NEXT: s_add_u32 s0, s2, s10 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: s_addc_u32 s1, s3, s10 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc -; GCN-NEXT: s_xor_b64 s[14:15], s[0:1], s[10:11] -; GCN-NEXT: v_mul_lo_u32 v3, s14, v2 -; GCN-NEXT: v_mul_hi_u32 v4, s14, v0 -; GCN-NEXT: v_mul_hi_u32 v5, s14, v2 -; GCN-NEXT: v_mul_hi_u32 v6, s15, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s15, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v5, s15, v0 -; GCN-NEXT: v_mul_hi_u32 v0, s15, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v7, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc +; GCN-NEXT: v_mul_lo_u32 v7, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 +; GCN-NEXT: v_mul_lo_u32 v4, s1, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_mul_lo_u32 v3, s0, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 +; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v2 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v7, v3 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v6, vcc +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc +; GCN-NEXT: s_add_u32 s0, s2, s10 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: s_addc_u32 s1, s3, s10 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc +; GCN-NEXT: s_xor_b64 s[14:15], s[0:1], s[10:11] +; GCN-NEXT: v_mul_lo_u32 v2, s14, v1 +; GCN-NEXT: v_mul_hi_u32 v3, s14, v0 +; GCN-NEXT: v_mul_hi_u32 v4, s14, v1 +; GCN-NEXT: v_mul_hi_u32 v5, s15, v1 +; GCN-NEXT: v_mul_lo_u32 v1, s15, v1 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v4, s15, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s15, v0 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v6, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 ; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 @@ -1290,7 +1287,6 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-LABEL: s_test_srem_k_num_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) @@ -1309,64 +1305,64 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 -; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 -; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 -; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s2, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s2, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s3, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_mul_lo_u32 v5, s2, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v4 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v7, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s2, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s2, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s3, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s2, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v3 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v5, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc -; GCN-NEXT: v_mul_lo_u32 v3, v1, 24 +; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc +; GCN-NEXT: v_mov_b32_e32 v3, s9 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc ; GCN-NEXT: v_mul_lo_u32 v1, s9, v0 ; GCN-NEXT: v_mul_hi_u32 v2, s8, v0 ; GCN-NEXT: v_mul_lo_u32 v0, s8, v0 -; GCN-NEXT: v_mov_b32_e32 v3, s9 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v1 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 @@ -1505,7 +1501,6 @@ define i64 @v_test_srem_k_num_i64(i64 %x) { ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc ; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 @@ -1519,20 +1514,20 @@ define i64 @v_test_srem_k_num_i64(i64 %x) { ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; GCN-NEXT: v_mul_lo_u32 v7, v4, v2 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GCN-NEXT: v_mul_lo_u32 v9, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v7 -; GCN-NEXT: v_mul_hi_u32 v8, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v13, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v8, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v7 +; GCN-NEXT: v_mul_hi_u32 v10, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v8, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc +; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v11, vcc ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3 @@ -1548,20 +1543,20 @@ define i64 @v_test_srem_k_num_i64(i64 %x) { ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v5 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v12, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v11, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 ; GCN-NEXT: v_mul_hi_u32 v2, v2, 24 ; GCN-NEXT: v_mul_hi_u32 v3, v3, 24 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v12, v3, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc ; GCN-NEXT: v_mul_lo_u32 v3, v1, v2 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v0, v2 @@ -1705,7 +1700,6 @@ define i64 @v_test_srem_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc ; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: s_mov_b32 s4, 0x8000 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 @@ -1720,20 +1714,20 @@ define i64 @v_test_srem_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 ; GCN-NEXT: v_mul_lo_u32 v7, v4, v2 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GCN-NEXT: v_mul_lo_u32 v9, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v7 -; GCN-NEXT: v_mul_hi_u32 v8, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v13, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v8, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v7 +; GCN-NEXT: v_mul_hi_u32 v10, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 -; GCN-NEXT: v_add_i32_e32 v9, vcc, v10, v9 +; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v10, v3, v7 ; GCN-NEXT: v_mul_hi_u32 v7, v3, v7 -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v8, vcc -; GCN-NEXT: v_add_i32_e32 v9, vcc, v9, v10 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc +; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v9, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v11, vcc ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3 @@ -1749,20 +1743,20 @@ define i64 @v_test_srem_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v5 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v12, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v11, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; GCN-NEXT: v_lshrrev_b32_e32 v4, 17, v3 ; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3 ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v12, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc ; GCN-NEXT: v_mul_lo_u32 v3, v1, v2 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v0, v2 @@ -1963,17 +1957,16 @@ define i64 @v_test_srem_pow2_k_den_i64(i64 %x) { ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 -; GCN-IR-NEXT: v_and_b32_e32 v15, 0x8000, v12 +; GCN-IR-NEXT: v_and_b32_e32 v14, 0x8000, v12 ; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8 ; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9] ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 -; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 -; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v15 +; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v14 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v13 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 -; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v14, s[4:5] +; GCN-IR-NEXT: v_subbrev_u32_e64 v11, s[4:5], 0, v11, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll index d1ed80f2b9dd..c58b102981be 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv.ll @@ -2487,7 +2487,6 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; SI-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000 ; SI-NEXT: v_rcp_f32_e32 v2, v2 ; SI-NEXT: s_mov_b32 s4, 0xfffe7960 -; SI-NEXT: v_mov_b32_e32 v10, 0 ; SI-NEXT: v_mov_b32_e32 v9, 0 ; SI-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; SI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 @@ -2500,20 +2499,20 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; SI-NEXT: v_mul_lo_u32 v6, v2, s4 ; SI-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4 ; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; SI-NEXT: v_mul_lo_u32 v7, v2, v4 -; SI-NEXT: v_mul_hi_u32 v8, v2, v6 -; SI-NEXT: v_mul_hi_u32 v5, v2, v4 -; SI-NEXT: v_mul_hi_u32 v11, v3, v4 +; SI-NEXT: v_mul_lo_u32 v5, v2, v4 +; SI-NEXT: v_mul_hi_u32 v7, v2, v6 +; SI-NEXT: v_mul_hi_u32 v8, v2, v4 +; SI-NEXT: v_mul_hi_u32 v10, v3, v4 ; SI-NEXT: v_mul_lo_u32 v4, v3, v4 -; SI-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; SI-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; SI-NEXT: v_mul_lo_u32 v8, v3, v6 ; SI-NEXT: v_mul_hi_u32 v6, v3, v6 -; SI-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc -; SI-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; SI-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc -; SI-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; SI-NEXT: v_add_i32_e32 v5, vcc, v5, v8 +; SI-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; SI-NEXT: v_addc_u32_e32 v6, vcc, v10, v9, vcc ; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; SI-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; SI-NEXT: v_mul_hi_u32 v4, v2, s4 @@ -2525,17 +2524,17 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; SI-NEXT: v_mul_lo_u32 v5, v2, v4 ; SI-NEXT: v_mul_hi_u32 v7, v2, v6 ; SI-NEXT: v_mul_hi_u32 v8, v2, v4 -; SI-NEXT: v_mul_hi_u32 v11, v3, v4 +; SI-NEXT: v_mul_hi_u32 v10, v3, v4 ; SI-NEXT: v_mul_lo_u32 v4, v3, v4 ; SI-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; SI-NEXT: v_addc_u32_e32 v7, vcc, v10, v8, vcc +; SI-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; SI-NEXT: v_mul_lo_u32 v8, v3, v6 ; SI-NEXT: v_mul_hi_u32 v6, v3, v6 ; SI-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; SI-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc -; SI-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; SI-NEXT: v_addc_u32_e32 v6, vcc, v10, v9, vcc ; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; SI-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; SI-NEXT: v_mul_lo_u32 v4, v0, v3 @@ -2544,14 +2543,14 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; SI-NEXT: v_mul_hi_u32 v7, v1, v3 ; SI-NEXT: v_mul_lo_u32 v3, v1, v3 ; SI-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; SI-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; SI-NEXT: v_mul_lo_u32 v6, v1, v2 ; SI-NEXT: v_mul_hi_u32 v2, v1, v2 ; SI-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; SI-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc ; SI-NEXT: v_addc_u32_e32 v4, vcc, v7, v9, vcc ; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; SI-NEXT: v_addc_u32_e32 v3, vcc, v10, v4, vcc +; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; SI-NEXT: v_mul_lo_u32 v4, v3, s4 ; SI-NEXT: v_mul_hi_u32 v5, v2, s4 ; SI-NEXT: v_mul_lo_u32 v6, v2, s4 @@ -2588,7 +2587,6 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; VI-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000 ; VI-NEXT: v_rcp_f32_e32 v2, v2 ; VI-NEXT: s_mov_b32 s4, 0xfffe7960 -; VI-NEXT: v_mov_b32_e32 v10, 0 ; VI-NEXT: v_mov_b32_e32 v9, 0 ; VI-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; VI-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 @@ -2601,20 +2599,20 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; VI-NEXT: v_mul_lo_u32 v6, v2, s4 ; VI-NEXT: v_subrev_u32_e32 v4, vcc, v2, v4 ; VI-NEXT: v_add_u32_e32 v4, vcc, v5, v4 -; VI-NEXT: v_mul_lo_u32 v7, v2, v4 -; VI-NEXT: v_mul_hi_u32 v8, v2, v6 -; VI-NEXT: v_mul_hi_u32 v5, v2, v4 -; VI-NEXT: v_mul_hi_u32 v11, v3, v4 +; VI-NEXT: v_mul_lo_u32 v5, v2, v4 +; VI-NEXT: v_mul_hi_u32 v7, v2, v6 +; VI-NEXT: v_mul_hi_u32 v8, v2, v4 +; VI-NEXT: v_mul_hi_u32 v10, v3, v4 ; VI-NEXT: v_mul_lo_u32 v4, v3, v4 -; VI-NEXT: v_add_u32_e32 v7, vcc, v8, v7 +; VI-NEXT: v_add_u32_e32 v5, vcc, v7, v5 +; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; VI-NEXT: v_mul_lo_u32 v8, v3, v6 ; VI-NEXT: v_mul_hi_u32 v6, v3, v6 -; VI-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc -; VI-NEXT: v_add_u32_e32 v7, vcc, v7, v8 -; VI-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc -; VI-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v8 +; VI-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; VI-NEXT: v_addc_u32_e32 v6, vcc, v10, v9, vcc ; VI-NEXT: v_add_u32_e32 v4, vcc, v5, v4 -; VI-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; VI-NEXT: v_mul_hi_u32 v4, v2, s4 @@ -2626,17 +2624,17 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; VI-NEXT: v_mul_lo_u32 v5, v2, v4 ; VI-NEXT: v_mul_hi_u32 v7, v2, v6 ; VI-NEXT: v_mul_hi_u32 v8, v2, v4 -; VI-NEXT: v_mul_hi_u32 v11, v3, v4 +; VI-NEXT: v_mul_hi_u32 v10, v3, v4 ; VI-NEXT: v_mul_lo_u32 v4, v3, v4 ; VI-NEXT: v_add_u32_e32 v5, vcc, v7, v5 -; VI-NEXT: v_addc_u32_e32 v7, vcc, v10, v8, vcc +; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; VI-NEXT: v_mul_lo_u32 v8, v3, v6 ; VI-NEXT: v_mul_hi_u32 v6, v3, v6 ; VI-NEXT: v_add_u32_e32 v5, vcc, v5, v8 ; VI-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc -; VI-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; VI-NEXT: v_addc_u32_e32 v6, vcc, v10, v9, vcc ; VI-NEXT: v_add_u32_e32 v4, vcc, v5, v4 -; VI-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; VI-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; VI-NEXT: v_mul_lo_u32 v4, v0, v3 @@ -2645,14 +2643,14 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; VI-NEXT: v_mul_hi_u32 v7, v1, v3 ; VI-NEXT: v_mul_lo_u32 v3, v1, v3 ; VI-NEXT: v_add_u32_e32 v4, vcc, v5, v4 -; VI-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; VI-NEXT: v_mul_lo_u32 v6, v1, v2 ; VI-NEXT: v_mul_hi_u32 v2, v1, v2 ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 ; VI-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc ; VI-NEXT: v_addc_u32_e32 v4, vcc, v7, v9, vcc ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v3 -; VI-NEXT: v_addc_u32_e32 v3, vcc, v10, v4, vcc +; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; VI-NEXT: v_mul_lo_u32 v4, v3, s4 ; VI-NEXT: v_mul_hi_u32 v5, v2, s4 ; VI-NEXT: v_mul_lo_u32 v6, v2, s4 @@ -2689,7 +2687,6 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x47c35000 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 ; GCN-NEXT: s_mov_b32 s4, 0xfffe7960 -; GCN-NEXT: v_mov_b32_e32 v10, 0 ; GCN-NEXT: v_mov_b32_e32 v9, 0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 @@ -2702,20 +2699,20 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; GCN-NEXT: v_mul_lo_u32 v6, v2, s4 ; GCN-NEXT: v_subrev_u32_e32 v4, vcc, v2, v4 ; GCN-NEXT: v_add_u32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v5, v2, v4 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_u32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_add_u32_e32 v5, vcc, v7, v5 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc -; GCN-NEXT: v_add_u32_e32 v7, vcc, v7, v8 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; GCN-NEXT: v_add_u32_e32 v5, vcc, v5, v8 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v9, vcc ; GCN-NEXT: v_add_u32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; GCN-NEXT: v_mul_hi_u32 v4, v2, s4 @@ -2727,17 +2724,17 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; GCN-NEXT: v_mul_lo_u32 v5, v2, v4 ; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v2, v4 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v4 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_add_u32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v10, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_add_u32_e32 v5, vcc, v5, v8 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v9, vcc ; GCN-NEXT: v_add_u32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v0, v3 @@ -2746,14 +2743,14 @@ define i64 @v_test_udiv64_mulhi_fold(i64 %arg) { ; GCN-NEXT: v_mul_hi_u32 v7, v1, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 ; GCN-NEXT: v_add_u32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v1, v2 ; GCN-NEXT: v_mul_hi_u32 v2, v1, v2 ; GCN-NEXT: v_add_u32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v9, vcc ; GCN-NEXT: v_add_u32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v10, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v3, s4 ; GCN-NEXT: v_mul_hi_u32 v5, v2, s4 ; GCN-NEXT: v_mul_lo_u32 v6, v2, s4 diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll index d5291f792f26..f9d6fa00ce7a 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll @@ -6,7 +6,6 @@ define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 % ; GCN-LABEL: s_test_udiv_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd -; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 @@ -19,71 +18,71 @@ define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 % ; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s4, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v7, s5, v0 -; GCN-NEXT: v_mul_lo_u32 v6, s4, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 -; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc -; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s4, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s5, v0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_mul_lo_u32 v5, s4, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v4 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 -; GCN-NEXT: v_mul_hi_u32 v6, s2, v3 -; GCN-NEXT: v_mul_hi_u32 v7, s3, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s3, v3 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_mul_lo_u32 v6, s3, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s5, v0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s4, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v3 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s2, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s2, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s2, v2 +; GCN-NEXT: v_mul_hi_u32 v6, s3, v2 +; GCN-NEXT: v_mul_lo_u32 v2, s3, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s3, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 ; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_mul_lo_u32 v2, s8, v1 ; GCN-NEXT: v_mul_hi_u32 v3, s8, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s9, v0 @@ -224,7 +223,6 @@ define i64 @v_test_udiv_i64(i64 %x, i64 %y) { ; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc ; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GCN-NEXT: v_rcp_f32_e32 v4, v4 -; GCN-NEXT: v_mov_b32_e32 v14, 0 ; GCN-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 @@ -238,20 +236,20 @@ define i64 @v_test_udiv_i64(i64 %x, i64 %y) { ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; GCN-NEXT: v_mul_lo_u32 v9, v6, v4 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 -; GCN-NEXT: v_mul_hi_u32 v12, v4, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v4, v8 -; GCN-NEXT: v_mul_hi_u32 v15, v5, v8 +; GCN-NEXT: v_mul_lo_u32 v10, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v11, v4, v9 +; GCN-NEXT: v_mul_hi_u32 v12, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v14, v5, v8 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc ; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 ; GCN-NEXT: v_mul_hi_u32 v9, v5, v9 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc +; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v12 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v13, vcc ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v6, v5 @@ -267,13 +265,13 @@ define i64 @v_test_udiv_i64(i64 %x, i64 %y) { ; GCN-NEXT: v_mul_lo_u32 v6, v5, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v5, v7 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v14, v12, vcc +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc ; GCN-NEXT: v_mul_lo_u32 v7, v5, v7 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v0, v5 @@ -282,14 +280,14 @@ define i64 @v_test_udiv_i64(i64 %x, i64 %y) { ; GCN-NEXT: v_mul_hi_u32 v9, v1, v5 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v5 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v13, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v2, v5 ; GCN-NEXT: v_mul_hi_u32 v7, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v8, v3, v4 @@ -701,7 +699,6 @@ define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 ; GCN-NEXT: s_load_dword s8, s[0:1], 0xb ; GCN-NEXT: s_load_dword s0, s[0:1], 0xc -; GCN-NEXT: v_mov_b32_e32 v9, 0 ; GCN-NEXT: v_mov_b32_e32 v8, 0 ; GCN-NEXT: v_mac_f32_e32 v1, 0x4f800000, v2 ; GCN-NEXT: v_rcp_f32_e32 v1, v1 @@ -724,20 +721,20 @@ define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v1 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v6, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v7, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v3 +; GCN-NEXT: v_mul_lo_u32 v5, v1, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v7, v1, v3 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc ; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v2, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc -; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v8, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc ; GCN-NEXT: v_mul_lo_u32 v3, s0, v2 @@ -747,19 +744,19 @@ define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 ; GCN-NEXT: v_mul_lo_u32 v4, s0, v1 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GCN-NEXT: v_mul_lo_u32 v7, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v10, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v11, v1, v3 +; GCN-NEXT: v_mul_hi_u32 v9, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v10, v1, v3 ; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 ; GCN-NEXT: v_mul_hi_u32 v5, v2, v3 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v9, v11, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v10, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v6, vcc ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 ; GCN-NEXT: v_mov_b32_e32 v3, s8 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc @@ -769,12 +766,12 @@ define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 ; GCN-NEXT: v_mul_hi_u32 v2, v3, v2 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v2, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v8, vcc ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v2, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v1 ; GCN-NEXT: v_add_i32_e32 v4, vcc, 2, v1 @@ -914,7 +911,6 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-LABEL: s_test_udiv_k_num_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) @@ -926,94 +922,94 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s4, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v7, s5, v0 -; GCN-NEXT: v_mul_lo_u32 v6, s4, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 -; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v3, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s4, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s5, v0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_mul_lo_u32 v5, s4, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v4 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v7, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s4, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s5, v0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s4, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v3 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v5, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc -; GCN-NEXT: v_mul_lo_u32 v3, v1, 24 +; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 -; GCN-NEXT: v_mov_b32_e32 v5, s3 +; GCN-NEXT: v_mov_b32_e32 v4, s3 ; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc ; GCN-NEXT: v_mul_lo_u32 v1, s3, v0 -; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; GCN-NEXT: v_mul_lo_u32 v3, s2, v0 -; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v1 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v3 -; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc -; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3 -; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5 +; GCN-NEXT: v_mul_hi_u32 v2, s2, v0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GCN-NEXT: v_mul_lo_u32 v2, s2, v0 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, 24, v2 +; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc +; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v2 +; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v3 ; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] -; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 -; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1] -; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 +; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v4 +; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] +; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v3 +; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1] +; GCN-NEXT: v_add_i32_e64 v4, s[0:1], 2, v0 +; GCN-NEXT: v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1] +; GCN-NEXT: v_add_i32_e64 v6, s[0:1], 1, v0 +; GCN-NEXT: v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1] ; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1] +; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 ; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 -; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc +; GCN-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 +; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc -; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc ; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc -; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] +; GCN-NEXT: v_cndmask_b32_e64 v2, v6, v4, s[0:1] +; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm @@ -1112,7 +1108,6 @@ define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc ; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 @@ -1126,20 +1121,20 @@ define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_mul_lo_u32 v9, v4, v2 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v9 -; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v13, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v9 +; GCN-NEXT: v_mul_hi_u32 v10, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v10, v3, v9 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v9 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v7, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v11, vcc ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3 @@ -1155,13 +1150,13 @@ define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v5 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v12, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v11, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v3, v5, vcc ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 @@ -1181,9 +1176,9 @@ define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v1 ; GCN-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[4:5] ; GCN-NEXT: v_add_i32_e64 v6, s[4:5], 2, v2 -; GCN-NEXT: v_addc_u32_e64 v7, s[4:5], 0, v12, s[4:5] +; GCN-NEXT: v_addc_u32_e64 v7, s[4:5], 0, 0, s[4:5] ; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 1, v2 -; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v12, s[4:5] +; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, 0, s[4:5] ; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc ; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 ; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1 @@ -1336,24 +1331,23 @@ define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) { ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 -; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v4 +; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 -; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v7 +; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6 ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v4 -; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v9 -; GCN-IR-NEXT: v_and_b32_e32 v11, 0x8000, v9 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0 ; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 +; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc +; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7 +; GCN-IR-NEXT: v_and_b32_e32 v7, 0x8000, v7 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v0, v9 -; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 -; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v7, v11 +; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v8, v6, s[4:5] +; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] @@ -1381,37 +1375,37 @@ define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: s_movk_i32 s4, 0xffe8 -; GCN-NEXT: v_mov_b32_e32 v8, 0 ; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: v_mul_hi_u32 v2, v0, s4 ; GCN-NEXT: v_mul_lo_u32 v3, v1, s4 ; GCN-NEXT: v_mul_lo_u32 v4, v0, s4 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v3, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 +; GCN-NEXT: v_mul_lo_u32 v3, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v5, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GCN-NEXT: v_mul_hi_u32 v2, v0, s4 @@ -1423,18 +1417,17 @@ define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-NEXT: v_mul_lo_u32 v3, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 +; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 ; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 -; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 @@ -1443,14 +1436,14 @@ define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-NEXT: v_mul_hi_u32 v5, s3, v1 ; GCN-NEXT: v_mul_lo_u32 v1, s3, v1 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v1, 24 ; GCN-NEXT: v_mul_hi_u32 v5, v0, 24 ; GCN-NEXT: v_add_i32_e32 v2, vcc, 2, v0 @@ -1567,7 +1560,6 @@ define i64 @v_test_udiv_k_den_i64(i64 %x) { ; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x41c00000 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 ; GCN-NEXT: s_movk_i32 s4, 0xffe8 -; GCN-NEXT: v_mov_b32_e32 v10, 0 ; GCN-NEXT: v_mov_b32_e32 v9, 0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 @@ -1580,20 +1572,20 @@ define i64 @v_test_udiv_k_den_i64(i64 %x) { ; GCN-NEXT: v_mul_lo_u32 v6, v2, s4 ; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v5, v2, v4 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc -; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v9, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; GCN-NEXT: v_mul_hi_u32 v4, v2, s4 @@ -1604,17 +1596,17 @@ define i64 @v_test_udiv_k_den_i64(i64 %x) { ; GCN-NEXT: v_mul_lo_u32 v5, v2, v4 ; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v2, v4 -; GCN-NEXT: v_mul_hi_u32 v11, v3, v4 +; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v10, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v9, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v0, v3 @@ -1623,14 +1615,14 @@ define i64 @v_test_udiv_k_den_i64(i64 %x) { ; GCN-NEXT: v_mul_hi_u32 v7, v1, v3 ; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v1, v2 ; GCN-NEXT: v_mul_hi_u32 v2, v1, v2 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v9, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v10, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 ; GCN-NEXT: v_mul_hi_u32 v5, v2, 24 ; GCN-NEXT: v_mul_lo_u32 v6, v2, 24 diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll index 3d501dc4074e..07552e7153bf 100644 --- a/llvm/test/CodeGen/AMDGPU/urem64.ll +++ b/llvm/test/CodeGen/AMDGPU/urem64.ll @@ -7,7 +7,6 @@ define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 % ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 -; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) @@ -21,69 +20,69 @@ define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 % ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_mov_b32 s5, s9 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s0, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s0, v0 -; GCN-NEXT: v_mul_lo_u32 v7, s1, v0 -; GCN-NEXT: v_mul_lo_u32 v6, s0, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 -; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc -; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s0, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s0, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s0, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s0, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s1, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_mul_lo_u32 v5, s0, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v4 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s10, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 -; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 -; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 -; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s0, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s0, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s1, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s0, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v3 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s10, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s10, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s10, v2 +; GCN-NEXT: v_mul_hi_u32 v6, s11, v2 +; GCN-NEXT: v_mul_lo_u32 v2, s11, v2 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 ; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 @@ -234,7 +233,6 @@ define i64 @v_test_urem_i64(i64 %x, i64 %y) { ; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc ; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GCN-NEXT: v_rcp_f32_e32 v4, v4 -; GCN-NEXT: v_mov_b32_e32 v14, 0 ; GCN-NEXT: v_mov_b32_e32 v13, 0 ; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 @@ -248,20 +246,20 @@ define i64 @v_test_urem_i64(i64 %x, i64 %y) { ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; GCN-NEXT: v_mul_lo_u32 v9, v6, v4 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 -; GCN-NEXT: v_mul_hi_u32 v12, v4, v9 -; GCN-NEXT: v_mul_hi_u32 v10, v4, v8 -; GCN-NEXT: v_mul_hi_u32 v15, v5, v8 +; GCN-NEXT: v_mul_lo_u32 v10, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v11, v4, v9 +; GCN-NEXT: v_mul_hi_u32 v12, v4, v8 +; GCN-NEXT: v_mul_hi_u32 v14, v5, v8 ; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 -; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 +; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc ; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 ; GCN-NEXT: v_mul_hi_u32 v9, v5, v9 -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc -; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc +; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v12 +; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v13, vcc ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v6, v5 @@ -277,13 +275,13 @@ define i64 @v_test_urem_i64(i64 %x, i64 %y) { ; GCN-NEXT: v_mul_lo_u32 v6, v5, v6 ; GCN-NEXT: v_mul_hi_u32 v8, v5, v7 ; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 -; GCN-NEXT: v_addc_u32_e32 v11, vcc, v14, v12, vcc +; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc ; GCN-NEXT: v_mul_lo_u32 v7, v5, v7 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6 ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc ; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v0, v5 @@ -292,14 +290,14 @@ define i64 @v_test_urem_i64(i64 %x, i64 %y) { ; GCN-NEXT: v_mul_hi_u32 v9, v1, v5 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v5 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_mul_lo_u32 v8, v1, v4 ; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v13, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 ; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 ; GCN-NEXT: v_mul_lo_u32 v7, v3, v4 @@ -737,7 +735,6 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-LABEL: s_test_urem_k_num_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: s_mov_b32 s11, 0xf000 ; GCN-NEXT: s_mov_b32 s10, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) @@ -751,64 +748,64 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: s_mov_b32 s9, s5 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v2, v2 +; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s0, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s0, v0 -; GCN-NEXT: v_mul_lo_u32 v7, s1, v0 -; GCN-NEXT: v_mul_lo_u32 v6, s0, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 -; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v3, v6 -; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 -; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc -; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s0, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s0, v0 +; GCN-NEXT: v_mul_lo_u32 v3, s0, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s0, v0 ; GCN-NEXT: v_mul_lo_u32 v6, s1, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_mul_lo_u32 v5, s0, v0 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 -; GCN-NEXT: v_mul_lo_u32 v8, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v9, v0, v5 -; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v4 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v2, v10, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 +; GCN-NEXT: v_mul_hi_u32 v4, v0, v5 +; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v7, v2, v5 +; GCN-NEXT: v_mul_lo_u32 v5, v2, v5 +; GCN-NEXT: v_mul_hi_u32 v9, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s0, v2 +; GCN-NEXT: v_mul_hi_u32 v4, s0, v0 +; GCN-NEXT: v_mul_lo_u32 v5, s1, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_mul_lo_u32 v4, s0, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_mul_lo_u32 v7, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v0, v4 +; GCN-NEXT: v_mul_hi_u32 v9, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v2, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v2, v4 +; GCN-NEXT: v_mul_hi_u32 v5, v2, v3 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc +; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v5, v1, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc -; GCN-NEXT: v_mul_lo_u32 v3, v1, 24 +; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 ; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 ; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc +; GCN-NEXT: v_mov_b32_e32 v3, s7 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc ; GCN-NEXT: v_mul_lo_u32 v1, s7, v0 ; GCN-NEXT: v_mul_hi_u32 v2, s6, v0 ; GCN-NEXT: v_mul_lo_u32 v0, s6, v0 -; GCN-NEXT: v_mov_b32_e32 v3, s7 ; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v1 ; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 @@ -936,76 +933,75 @@ define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) ; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: s_movk_i32 s4, 0xffe8 -; GCN-NEXT: v_mov_b32_e32 v8, 0 -; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_mov_b32_e32 v2, 0 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: v_mul_hi_u32 v2, v0, s4 -; GCN-NEXT: v_mul_lo_u32 v3, v1, s4 -; GCN-NEXT: v_mul_lo_u32 v4, v0, s4 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v3, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 -; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc -; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v2, v0, s4 -; GCN-NEXT: v_mul_lo_u32 v3, v1, s4 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s4 +; GCN-NEXT: v_mul_lo_u32 v5, v1, s4 ; GCN-NEXT: v_mul_lo_u32 v4, v0, s4 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v5, v0, v4 -; GCN-NEXT: v_mul_hi_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc -; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 ; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 -; GCN-NEXT: v_mul_hi_u32 v4, s2, v1 -; GCN-NEXT: v_mul_hi_u32 v5, s3, v1 +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v0, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 +; GCN-NEXT: v_mul_lo_u32 v5, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v1, v3 +; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc +; GCN-NEXT: v_mul_lo_u32 v7, v1, v4 +; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 +; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v2, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc +; GCN-NEXT: v_mul_hi_u32 v3, v0, s4 +; GCN-NEXT: v_mul_lo_u32 v4, v1, s4 +; GCN-NEXT: v_mul_lo_u32 v5, v0, s4 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: v_subrev_i32_e32 v3, vcc, v0, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 +; GCN-NEXT: v_mul_lo_u32 v4, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v6, v0, v5 +; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 +; GCN-NEXT: v_mul_hi_u32 v8, v1, v3 +; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4 +; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc +; GCN-NEXT: v_mul_lo_u32 v7, v1, v5 +; GCN-NEXT: v_mul_hi_u32 v5, v1, v5 +; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, v8, v2, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v4, vcc +; GCN-NEXT: v_mul_lo_u32 v3, s2, v1 +; GCN-NEXT: v_mul_hi_u32 v4, s2, v0 +; GCN-NEXT: v_mul_hi_u32 v5, s2, v1 +; GCN-NEXT: v_mul_hi_u32 v6, s3, v1 ; GCN-NEXT: v_mul_lo_u32 v1, s3, v1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc +; GCN-NEXT: v_mul_lo_u32 v5, s3, v0 ; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 +; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v6, v2, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc ; GCN-NEXT: v_mul_lo_u32 v1, v1, 24 ; GCN-NEXT: v_mul_hi_u32 v2, v0, 24 ; GCN-NEXT: v_mul_lo_u32 v0, v0, 24 @@ -1137,7 +1133,6 @@ define i64 @v_test_urem_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc ; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 ; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mov_b32_e32 v12, 0 ; GCN-NEXT: v_mov_b32_e32 v11, 0 ; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 @@ -1151,20 +1146,20 @@ define i64 @v_test_urem_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_mul_lo_u32 v9, v4, v2 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GCN-NEXT: v_mul_lo_u32 v8, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v10, v2, v9 -; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 -; GCN-NEXT: v_mul_hi_u32 v13, v3, v6 +; GCN-NEXT: v_mul_lo_u32 v7, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v8, v2, v9 +; GCN-NEXT: v_mul_hi_u32 v10, v2, v6 +; GCN-NEXT: v_mul_hi_u32 v12, v3, v6 ; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 -; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 +; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 +; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v10, v3, v9 ; GCN-NEXT: v_mul_hi_u32 v9, v3, v9 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v7, vcc -; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc -; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc +; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10 +; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v9, vcc +; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v11, vcc ; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc +; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc ; GCN-NEXT: v_mul_lo_u32 v6, v4, v3 @@ -1180,13 +1175,13 @@ define i64 @v_test_urem_pow2_k_num_i64(i64 %x) { ; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 ; GCN-NEXT: v_mul_hi_u32 v6, v3, v5 ; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GCN-NEXT: v_addc_u32_e32 v9, vcc, v12, v10, vcc +; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc ; GCN-NEXT: v_mul_lo_u32 v5, v3, v5 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc ; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v11, vcc ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v3, v5, vcc ; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 @@ -1373,17 +1368,16 @@ define i64 @v_test_urem_pow2_k_den_i64(i64 %x) { ; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 -; GCN-IR-NEXT: v_and_b32_e32 v13, 0x8000, v10 +; GCN-IR-NEXT: v_and_b32_e32 v12, 0x8000, v10 ; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10 -; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 -; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v13 +; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v12 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 -; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v12, s[4:5] +; GCN-IR-NEXT: v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5] ; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] ; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]