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[X86] Prefer locked stack op over mfence for seq_cst 64-bit stores on 32-bit targets 

This is a follow on to D58632, with the same logic. Given a memory operation which needs ordering, but doesn't need to modify any particular address, prefer to use a locked stack op over an mfence.

Differential Revision: https://reviews.llvm.org/D61863

llvm-svn: 360649
This commit is contained in:
Philip Reames 2019-05-14 04:43:37 +00:00
parent e1cb2c0f40
commit 3098e44daa
3 changed files with 6 additions and 5 deletions
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5
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -26456,9 +26456,10 @@ static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG,
Ops, MVT::i64,
Node->getMemOperand());
// If this is a sequentially consistent store, also emit an mfence.
// If this is a sequentially consistent store, also emit an appropriate
// barrier.
if (IsSeqCst)
Chain = DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Chain);
Chain = emitLockedStackOp(DAG, Subtarget, Chain, dl);
return Chain;
}

2
llvm/test/CodeGen/X86/atomic-load-store-wide.ll
View File

@ -11,7 +11,7 @@ define void @test1(i64* %ptr, i64 %val1) {
; SSE42-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE42-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE42-NEXT: movlps %xmm0, (%eax)
; SSE42-NEXT: mfence
; SSE42-NEXT: lock orl $0, (%esp)
; SSE42-NEXT: retl
;
; NOSSE-LABEL: test1:

4
llvm/test/CodeGen/X86/atomic-non-integer.ll
View File

@ -710,7 +710,7 @@ define void @store_double_seq_cst(double* %fptr, double %v) {
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movlps %xmm0, (%eax)
; X86-SSE2-NEXT: mfence
; X86-SSE2-NEXT: lock orl $0, (%esp)
; X86-SSE2-NEXT: retl
;
; X86-AVX-LABEL: store_double_seq_cst:
@ -718,7 +718,7 @@ define void @store_double_seq_cst(double* %fptr, double %v) {
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX-NEXT: vmovlps %xmm0, (%eax)
; X86-AVX-NEXT: mfence
; X86-AVX-NEXT: lock orl $0, (%esp)
; X86-AVX-NEXT: retl
;
; X86-NOSSE-LABEL: store_double_seq_cst: