forked from OSchip/llvm-project
Chris Lattner
parent
3ed3be3b4a
commit
3066beccb5
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@ -912,308 +912,9 @@ SDOperand X86TargetLowering::LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG,
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// X86-64 C Calling Convention implementation
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// FastCall Calling Convention implementation
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//===----------------------------------------------------------------------===//
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SDOperand
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X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
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unsigned NumArgs = Op.Val->getNumValues() - 1;
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SDOperand Root = Op.getOperand(0);
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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static const unsigned GPR64ArgRegs[] = {
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X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
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};
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static const unsigned XMMArgRegs[] = {
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X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
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X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
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};
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
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ArgLocs);
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for (unsigned i = 0; i != NumArgs; ++i) {
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MVT::ValueType ArgVT = Op.getValue(i).getValueType();
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unsigned ArgFlags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue();
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if (CC_X86_64_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
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assert(0 && "Unhandled argument type!");
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}
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SmallVector<SDOperand, 8> ArgValues;
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unsigned LastVal = ~0U;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
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// places.
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assert(VA.getValNo() != LastVal &&
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"Don't support value assigned to multiple locs yet");
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LastVal = VA.getValNo();
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if (VA.isRegLoc()) {
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MVT::ValueType RegVT = VA.getLocVT();
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TargetRegisterClass *RC;
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if (RegVT == MVT::i32)
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RC = X86::GR32RegisterClass;
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else if (RegVT == MVT::i64)
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RC = X86::GR64RegisterClass;
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else if (RegVT == MVT::f32)
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RC = X86::FR32RegisterClass;
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else if (RegVT == MVT::f64)
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RC = X86::FR64RegisterClass;
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else {
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assert(MVT::isVector(RegVT));
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RC = X86::VR128RegisterClass;
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}
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SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT);
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AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
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// If this is an 8 or 16-bit value, it is really passed promoted to 32
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// bits. Insert an assert[sz]ext to capture this, then truncate to the
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// right size.
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if (VA.getLocInfo() == CCValAssign::SExt)
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ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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else if (VA.getLocInfo() == CCValAssign::ZExt)
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ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
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DAG.getValueType(VA.getValVT()));
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if (VA.getLocInfo() != CCValAssign::Full)
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ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
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ArgValues.push_back(ArgValue);
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} else {
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assert(VA.isMemLoc());
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// Create the nodes corresponding to a load from this parameter slot.
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
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VA.getLocMemOffset());
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SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
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ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
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}
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}
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unsigned StackSize = CCInfo.getNextStackOffset();
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first vararg value... for expansion of llvm.va_start.
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if (isVarArg) {
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unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
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unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
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// For X86-64, if there are vararg parameters that are passed via
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// registers, then we must store them to their spots on the stack so they
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// may be loaded by deferencing the result of va_next.
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VarArgsGPOffset = NumIntRegs * 8;
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VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
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VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
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RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
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// Store the integer parameter registers.
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SmallVector<SDOperand, 8> MemOps;
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SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
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SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
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DAG.getConstant(VarArgsGPOffset, getPointerTy()));
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for (; NumIntRegs != 6; ++NumIntRegs) {
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unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
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X86::GR64RegisterClass);
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SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
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SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
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MemOps.push_back(Store);
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FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
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DAG.getConstant(8, getPointerTy()));
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}
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// Now store the XMM (fp + vector) parameter registers.
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FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
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DAG.getConstant(VarArgsFPOffset, getPointerTy()));
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for (; NumXMMRegs != 8; ++NumXMMRegs) {
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unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
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X86::VR128RegisterClass);
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SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
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SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
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MemOps.push_back(Store);
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FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
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DAG.getConstant(16, getPointerTy()));
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}
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if (!MemOps.empty())
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
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&MemOps[0], MemOps.size());
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}
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ArgValues.push_back(Root);
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ReturnAddrIndex = 0; // No return address slot generated yet.
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BytesToPopOnReturn = 0; // Callee pops nothing.
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BytesCallerReserves = StackSize;
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// Return the new list of results.
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return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
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&ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
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}
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SDOperand
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X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
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unsigned CC) {
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SDOperand Chain = Op.getOperand(0);
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
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SDOperand Callee = Op.getOperand(4);
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unsigned NumOps = (Op.getNumOperands() - 5) / 2;
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CC, getTargetMachine(), ArgLocs);
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for (unsigned i = 0; i != NumOps; ++i) {
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MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType();
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unsigned ArgFlags =cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
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if (CC_X86_64_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
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assert(0 && "Unhandled argument type!");
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}
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
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SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
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SmallVector<SDOperand, 8> MemOpChains;
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SDOperand StackPtr;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
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// Promote the value if needed.
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switch (VA.getLocInfo()) {
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default: assert(0 && "Unknown loc info!");
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case CCValAssign::Full: break;
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case CCValAssign::SExt:
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Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
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break;
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case CCValAssign::ZExt:
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Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
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break;
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
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break;
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}
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if (VA.isRegLoc()) {
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
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} else {
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assert(VA.isMemLoc());
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if (StackPtr.Val == 0)
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StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
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SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
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PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
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MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
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}
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}
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token chain
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// and flag operands which copy the outgoing args into registers.
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SDOperand InFlag;
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
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Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
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InFlag);
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InFlag = Chain.getValue(1);
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}
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if (isVarArg) {
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// From AMD64 ABI document:
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// For calls that may call functions that use varargs or stdargs
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// (prototype-less calls or calls to functions containing ellipsis (...) in
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// the declaration) %al is used as hidden argument to specify the number
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// of SSE registers used. The contents of %al do not need to match exactly
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// the number of registers, but must be an ubound on the number of SSE
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// registers used and is in the range 0 - 8 inclusive.
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// Count the number of XMM registers allocated.
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static const unsigned XMMArgRegs[] = {
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X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
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X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
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};
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unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
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Chain = DAG.getCopyToReg(Chain, X86::AL,
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DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
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InFlag = Chain.getValue(1);
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}
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// If the callee is a GlobalAddress node (quite common, every direct call is)
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// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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// We should use extra load for direct calls to dllimported functions in
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// non-JIT mode.
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if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
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getTargetMachine(), true))
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Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
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} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
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Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
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// Returns a chain & a flag for retval copy to use.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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SmallVector<SDOperand, 8> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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// Add argument registers to the end of the list so that they are known live
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// into the call.
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for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
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Ops.push_back(DAG.getRegister(RegsToPass[i].first,
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RegsToPass[i].second.getValueType()));
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if (InFlag.Val)
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Ops.push_back(InFlag);
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// FIXME: Do not generate X86ISD::TAILCALL for now.
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Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
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NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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// Returns a flag for retval copy to use.
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NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
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Ops.clear();
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Ops.push_back(Chain);
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Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
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Ops.push_back(DAG.getConstant(0, getPointerTy()));
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Ops.push_back(InFlag);
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Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
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InFlag = Chain.getValue(1);
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// Handle result values, copying them out of physregs into vregs that we
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// return.
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return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
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}
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//===----------------------------------------------------------------------===//
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// Fast & FastCall Calling Convention implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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//
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// The X86 'fast' calling convention passes up to two integer arguments in
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// registers (an appropriate portion of EAX/EDX), passes arguments in C order,
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// and requires that the callee pop its arguments off the stack (allowing proper
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// tail calls), and has the same return value conventions as C calling convs.
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//
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// This calling convention always arranges for the callee pop value to be 8n+4
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// bytes, which is needed for tail recursion elimination and stack alignment
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// reasons.
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//
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// Note that this can be enhanced in the future to pass fp vals in registers
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// (when we have a global fp allocator) and do other tricks.
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//
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//===----------------------------------------------------------------------===//
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// The X86 'fastcall' calling convention passes up to two integer arguments in
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// The X86 'fastcall' calling convention passes up to two integer arguments in
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// registers (an appropriate portion of ECX/EDX), passes arguments in C order,
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// registers (an appropriate portion of ECX/EDX), passes arguments in C order,
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// and requires that the callee pop its arguments off the stack (allowing proper
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// and requires that the callee pop its arguments off the stack (allowing proper
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@ -1562,6 +1263,297 @@ SDOperand X86TargetLowering::LowerFastCCCallTo(SDOperand Op, SelectionDAG &DAG,
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return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
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return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
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}
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}
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//===----------------------------------------------------------------------===//
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// X86-64 C Calling Convention implementation
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//===----------------------------------------------------------------------===//
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SDOperand
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X86TargetLowering::LowerX86_64CCCArguments(SDOperand Op, SelectionDAG &DAG) {
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unsigned NumArgs = Op.Val->getNumValues() - 1;
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SDOperand Root = Op.getOperand(0);
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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||||||
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|
||||||
|
static const unsigned GPR64ArgRegs[] = {
|
||||||
|
X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
|
||||||
|
};
|
||||||
|
static const unsigned XMMArgRegs[] = {
|
||||||
|
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
|
||||||
|
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
|
||||||
|
};
|
||||||
|
|
||||||
|
SmallVector<CCValAssign, 16> ArgLocs;
|
||||||
|
CCState CCInfo(MF.getFunction()->getCallingConv(), getTargetMachine(),
|
||||||
|
ArgLocs);
|
||||||
|
|
||||||
|
for (unsigned i = 0; i != NumArgs; ++i) {
|
||||||
|
MVT::ValueType ArgVT = Op.getValue(i).getValueType();
|
||||||
|
unsigned ArgFlags = cast<ConstantSDNode>(Op.getOperand(3+i))->getValue();
|
||||||
|
if (CC_X86_64_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
|
||||||
|
assert(0 && "Unhandled argument type!");
|
||||||
|
}
|
||||||
|
|
||||||
|
SmallVector<SDOperand, 8> ArgValues;
|
||||||
|
unsigned LastVal = ~0U;
|
||||||
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
|
CCValAssign &VA = ArgLocs[i];
|
||||||
|
// TODO: If an arg is passed in two places (e.g. reg and stack), skip later
|
||||||
|
// places.
|
||||||
|
assert(VA.getValNo() != LastVal &&
|
||||||
|
"Don't support value assigned to multiple locs yet");
|
||||||
|
LastVal = VA.getValNo();
|
||||||
|
|
||||||
|
if (VA.isRegLoc()) {
|
||||||
|
MVT::ValueType RegVT = VA.getLocVT();
|
||||||
|
TargetRegisterClass *RC;
|
||||||
|
if (RegVT == MVT::i32)
|
||||||
|
RC = X86::GR32RegisterClass;
|
||||||
|
else if (RegVT == MVT::i64)
|
||||||
|
RC = X86::GR64RegisterClass;
|
||||||
|
else if (RegVT == MVT::f32)
|
||||||
|
RC = X86::FR32RegisterClass;
|
||||||
|
else if (RegVT == MVT::f64)
|
||||||
|
RC = X86::FR64RegisterClass;
|
||||||
|
else {
|
||||||
|
assert(MVT::isVector(RegVT));
|
||||||
|
RC = X86::VR128RegisterClass;
|
||||||
|
}
|
||||||
|
|
||||||
|
SDOperand ArgValue = DAG.getCopyFromReg(Root, VA.getLocReg(), RegVT);
|
||||||
|
AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
|
||||||
|
|
||||||
|
// If this is an 8 or 16-bit value, it is really passed promoted to 32
|
||||||
|
// bits. Insert an assert[sz]ext to capture this, then truncate to the
|
||||||
|
// right size.
|
||||||
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
||||||
|
ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
|
||||||
|
DAG.getValueType(VA.getValVT()));
|
||||||
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
||||||
|
ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
|
||||||
|
DAG.getValueType(VA.getValVT()));
|
||||||
|
|
||||||
|
if (VA.getLocInfo() != CCValAssign::Full)
|
||||||
|
ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
|
||||||
|
|
||||||
|
ArgValues.push_back(ArgValue);
|
||||||
|
} else {
|
||||||
|
assert(VA.isMemLoc());
|
||||||
|
|
||||||
|
// Create the nodes corresponding to a load from this parameter slot.
|
||||||
|
int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
|
||||||
|
VA.getLocMemOffset());
|
||||||
|
SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
|
||||||
|
ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned StackSize = CCInfo.getNextStackOffset();
|
||||||
|
|
||||||
|
// If the function takes variable number of arguments, make a frame index for
|
||||||
|
// the start of the first vararg value... for expansion of llvm.va_start.
|
||||||
|
if (isVarArg) {
|
||||||
|
unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 6);
|
||||||
|
unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
|
||||||
|
|
||||||
|
// For X86-64, if there are vararg parameters that are passed via
|
||||||
|
// registers, then we must store them to their spots on the stack so they
|
||||||
|
// may be loaded by deferencing the result of va_next.
|
||||||
|
VarArgsGPOffset = NumIntRegs * 8;
|
||||||
|
VarArgsFPOffset = 6 * 8 + NumXMMRegs * 16;
|
||||||
|
VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
|
||||||
|
RegSaveFrameIndex = MFI->CreateStackObject(6 * 8 + 8 * 16, 16);
|
||||||
|
|
||||||
|
// Store the integer parameter registers.
|
||||||
|
SmallVector<SDOperand, 8> MemOps;
|
||||||
|
SDOperand RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
|
||||||
|
SDOperand FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
|
||||||
|
DAG.getConstant(VarArgsGPOffset, getPointerTy()));
|
||||||
|
for (; NumIntRegs != 6; ++NumIntRegs) {
|
||||||
|
unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
|
||||||
|
X86::GR64RegisterClass);
|
||||||
|
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
|
||||||
|
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
||||||
|
MemOps.push_back(Store);
|
||||||
|
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
||||||
|
DAG.getConstant(8, getPointerTy()));
|
||||||
|
}
|
||||||
|
|
||||||
|
// Now store the XMM (fp + vector) parameter registers.
|
||||||
|
FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
|
||||||
|
DAG.getConstant(VarArgsFPOffset, getPointerTy()));
|
||||||
|
for (; NumXMMRegs != 8; ++NumXMMRegs) {
|
||||||
|
unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
|
||||||
|
X86::VR128RegisterClass);
|
||||||
|
SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
|
||||||
|
SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
|
||||||
|
MemOps.push_back(Store);
|
||||||
|
FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
|
||||||
|
DAG.getConstant(16, getPointerTy()));
|
||||||
|
}
|
||||||
|
if (!MemOps.empty())
|
||||||
|
Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
||||||
|
&MemOps[0], MemOps.size());
|
||||||
|
}
|
||||||
|
|
||||||
|
ArgValues.push_back(Root);
|
||||||
|
|
||||||
|
ReturnAddrIndex = 0; // No return address slot generated yet.
|
||||||
|
BytesToPopOnReturn = 0; // Callee pops nothing.
|
||||||
|
BytesCallerReserves = StackSize;
|
||||||
|
|
||||||
|
// Return the new list of results.
|
||||||
|
return DAG.getNode(ISD::MERGE_VALUES, Op.Val->getVTList(),
|
||||||
|
&ArgValues[0], ArgValues.size()).getValue(Op.ResNo);
|
||||||
|
}
|
||||||
|
|
||||||
|
SDOperand
|
||||||
|
X86TargetLowering::LowerX86_64CCCCallTo(SDOperand Op, SelectionDAG &DAG,
|
||||||
|
unsigned CC) {
|
||||||
|
SDOperand Chain = Op.getOperand(0);
|
||||||
|
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
|
||||||
|
bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
|
||||||
|
SDOperand Callee = Op.getOperand(4);
|
||||||
|
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
|
||||||
|
|
||||||
|
SmallVector<CCValAssign, 16> ArgLocs;
|
||||||
|
CCState CCInfo(CC, getTargetMachine(), ArgLocs);
|
||||||
|
|
||||||
|
for (unsigned i = 0; i != NumOps; ++i) {
|
||||||
|
MVT::ValueType ArgVT = Op.getOperand(5+2*i).getValueType();
|
||||||
|
unsigned ArgFlags =cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
|
||||||
|
if (CC_X86_64_C(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo))
|
||||||
|
assert(0 && "Unhandled argument type!");
|
||||||
|
}
|
||||||
|
|
||||||
|
// Get a count of how many bytes are to be pushed on the stack.
|
||||||
|
unsigned NumBytes = CCInfo.getNextStackOffset();
|
||||||
|
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
|
||||||
|
|
||||||
|
SmallVector<std::pair<unsigned, SDOperand>, 8> RegsToPass;
|
||||||
|
SmallVector<SDOperand, 8> MemOpChains;
|
||||||
|
|
||||||
|
SDOperand StackPtr;
|
||||||
|
|
||||||
|
// Walk the register/memloc assignments, inserting copies/loads.
|
||||||
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
||||||
|
CCValAssign &VA = ArgLocs[i];
|
||||||
|
SDOperand Arg = Op.getOperand(5+2*VA.getValNo());
|
||||||
|
|
||||||
|
// Promote the value if needed.
|
||||||
|
switch (VA.getLocInfo()) {
|
||||||
|
default: assert(0 && "Unknown loc info!");
|
||||||
|
case CCValAssign::Full: break;
|
||||||
|
case CCValAssign::SExt:
|
||||||
|
Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
|
||||||
|
break;
|
||||||
|
case CCValAssign::ZExt:
|
||||||
|
Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
|
||||||
|
break;
|
||||||
|
case CCValAssign::AExt:
|
||||||
|
Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (VA.isRegLoc()) {
|
||||||
|
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
||||||
|
} else {
|
||||||
|
assert(VA.isMemLoc());
|
||||||
|
if (StackPtr.Val == 0)
|
||||||
|
StackPtr = DAG.getRegister(getStackPtrReg(), getPointerTy());
|
||||||
|
SDOperand PtrOff = DAG.getConstant(VA.getLocMemOffset(), getPointerTy());
|
||||||
|
PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
|
||||||
|
MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!MemOpChains.empty())
|
||||||
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
|
||||||
|
&MemOpChains[0], MemOpChains.size());
|
||||||
|
|
||||||
|
// Build a sequence of copy-to-reg nodes chained together with token chain
|
||||||
|
// and flag operands which copy the outgoing args into registers.
|
||||||
|
SDOperand InFlag;
|
||||||
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
||||||
|
Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
|
||||||
|
InFlag);
|
||||||
|
InFlag = Chain.getValue(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (isVarArg) {
|
||||||
|
// From AMD64 ABI document:
|
||||||
|
// For calls that may call functions that use varargs or stdargs
|
||||||
|
// (prototype-less calls or calls to functions containing ellipsis (...) in
|
||||||
|
// the declaration) %al is used as hidden argument to specify the number
|
||||||
|
// of SSE registers used. The contents of %al do not need to match exactly
|
||||||
|
// the number of registers, but must be an ubound on the number of SSE
|
||||||
|
// registers used and is in the range 0 - 8 inclusive.
|
||||||
|
|
||||||
|
// Count the number of XMM registers allocated.
|
||||||
|
static const unsigned XMMArgRegs[] = {
|
||||||
|
X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
|
||||||
|
X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
|
||||||
|
};
|
||||||
|
unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
|
||||||
|
|
||||||
|
Chain = DAG.getCopyToReg(Chain, X86::AL,
|
||||||
|
DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
|
||||||
|
InFlag = Chain.getValue(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
// If the callee is a GlobalAddress node (quite common, every direct call is)
|
||||||
|
// turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
|
||||||
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
|
||||||
|
// We should use extra load for direct calls to dllimported functions in
|
||||||
|
// non-JIT mode.
|
||||||
|
if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
|
||||||
|
getTargetMachine(), true))
|
||||||
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
|
||||||
|
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
|
||||||
|
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
|
||||||
|
|
||||||
|
// Returns a chain & a flag for retval copy to use.
|
||||||
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
||||||
|
SmallVector<SDOperand, 8> Ops;
|
||||||
|
Ops.push_back(Chain);
|
||||||
|
Ops.push_back(Callee);
|
||||||
|
|
||||||
|
// Add argument registers to the end of the list so that they are known live
|
||||||
|
// into the call.
|
||||||
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
|
||||||
|
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
|
||||||
|
RegsToPass[i].second.getValueType()));
|
||||||
|
|
||||||
|
if (InFlag.Val)
|
||||||
|
Ops.push_back(InFlag);
|
||||||
|
|
||||||
|
// FIXME: Do not generate X86ISD::TAILCALL for now.
|
||||||
|
Chain = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
|
||||||
|
NodeTys, &Ops[0], Ops.size());
|
||||||
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
|
// Returns a flag for retval copy to use.
|
||||||
|
NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
|
||||||
|
Ops.clear();
|
||||||
|
Ops.push_back(Chain);
|
||||||
|
Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
|
||||||
|
Ops.push_back(DAG.getConstant(0, getPointerTy()));
|
||||||
|
Ops.push_back(InFlag);
|
||||||
|
Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
|
||||||
|
InFlag = Chain.getValue(1);
|
||||||
|
|
||||||
|
// Handle result values, copying them out of physregs into vregs that we
|
||||||
|
// return.
|
||||||
|
return SDOperand(LowerCallResult(Chain, InFlag, Op.Val, CC, DAG), Op.ResNo);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
// Other Lowering Hooks
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
|
||||||
SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
|
SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
|
||||||
if (ReturnAddrIndex == 0) {
|
if (ReturnAddrIndex == 0) {
|
||||||
// Set up a frame object for the return address.
|
// Set up a frame object for the return address.
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue