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getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 

llvm-svn: 28378
This commit is contained in:
Evan Cheng 2006-05-18 00:12:58 +00:00
parent 297e1cb10a
commit 305c49579c
18 changed files with 179 additions and 92 deletions
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3
llvm/lib/Target/ARM/ARM.td
View File

@ -40,9 +40,6 @@ def ARMInstrInfo : InstrInfo {
//===----------------------------------------------------------------------===//
def ARM : Target {
// FIXME: Specify callee-saved registers
let CalleeSavedRegisters = [];
// Pull in Instruction Info:
let InstructionSet = ARMInstrInfo;
}

11
llvm/lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -58,6 +58,17 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
return NULL;
}
const unsigned* ARMRegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = { 0 };
return CalleeSaveRegs;
}
const TargetRegisterClass* const *
ARMRegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
return CalleeSaveRegClasses;
}
void ARMRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {

4
llvm/lib/Target/ARM/ARMRegisterInfo.h
View File

@ -45,6 +45,10 @@ struct ARMRegisterInfo : public ARMGenRegisterInfo {
unsigned OpNum,
int FrameIndex) const;
const unsigned *getCalleeSaveRegs() const;
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;

11
llvm/lib/Target/Alpha/Alpha.td
View File

@ -65,17 +65,6 @@ def : Processor<"ev67" , Alpha21264Itineraries, [FeatureFIX, FeatureCIX]>;
def Alpha : Target {
let CalleeSavedRegisters =
//saved regs
[R9, R10, R11, R12, R13, R14,
//Frame pointer
// R15,
//return address
// R26,
//Stack Pointer
// R30,
F2, F3, F4, F5, F6, F7, F8, F9];
// Pull in Instruction Info:
let InstructionSet = AlphaInstrInfo;
}

27
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -145,6 +145,33 @@ void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
}
}
const unsigned* AlphaRegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = {
Alpha::R9, Alpha::R10,
Alpha::R11, Alpha::R12,
Alpha::R13, Alpha::R14,
Alpha::F2, Alpha::F3,
Alpha::F4, Alpha::F5,
Alpha::F6, Alpha::F7,
Alpha::F8, Alpha::F9, 0
};
return CalleeSaveRegs;
}
const TargetRegisterClass* const*
AlphaRegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
&Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
&Alpha::F8RCRegClass, &Alpha::F8RCRegClass,
&Alpha::F8RCRegClass, &Alpha::F8RCRegClass, 0
};
return CalleeSaveRegClasses;
}
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//

4
llvm/lib/Target/Alpha/AlphaRegisterInfo.h
View File

@ -42,6 +42,10 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
const unsigned *getCalleeSaveRegs() const;
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;

60
llvm/lib/Target/IA64/IA64.td
View File

@ -31,66 +31,6 @@ include "IA64InstrInfo.td"
def IA64InstrInfo : InstrInfo { }
def IA64 : Target {
// The following registers are always saved across calls:
let CalleeSavedRegisters =
//'preserved' GRs:
[
r5 // the 'frame pointer' (base pointer) reg
// We never generate references to these regs, so we don't need to declare
// that they are saved. In fact, we could just remove them entirely.
//r4, r6, r7,
//'special' GRs:
// r1, // global data pointer (GP) - XXX NOT callee saved, we do it ourselves
// r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves
// rp, // return branch register (rp/b0) - we do this ourselves
// **** r13 (thread pointer) we do not touch, ever. it's not here. ****//
//'stacked' GRs the RSE takes care of, we don't worry about
/* We don't want PEI::calculateCallerSavedRegisters to worry about them,
since the RSE takes care of them (and we determinethe appropriate
'alloc' instructions and save/restore ar.pfs ourselves, in instruction
selection)
**************************************************************************
* r32, r33, r34, r35,
* r36, r37, r38, r39, r40, r41, r42, r43, r44, r45, r46, r47,
* r48, r49, r50, r51, r52, r53, r54, r55, r56, r57, r58, r59,
* r60, r61, r62, r63, r64, r65, r66, r67, r68, r69, r70, r71,
* r72, r73, r74, r75, r76, r77, r78, r79, r80, r81, r82, r83,
* r84, r85, r86, r87, r88, r89, r90, r91, r92, r93, r94, r95,
* r96, r97, r98, r99, r100, r101, r102, r103, r104, r105, r106, r107,
* r108, r109, r110, r111, r112, r113, r114, r115, r116, r117, r118, r119,
* r120, r121, r122, r123, r124, r125, r126, r127,
**************************************************************************
*/
//'preserved' FP regs:
/* We never generate references to these regs, so we don't need to declare
* that they are saved. In fact, we could just remove them entirely.
* F2,F3,F4, F5,
* F16,F17,F18,F19,F20,F21,F22,F23,
* F24,F25,F26,F27,F28,F29,F30,F31,
*/
//'preserved' predicate regs:
/* We never generate references to these regs, so we don't need to declare
that they are saved. In fact, we could just remove them entirely.
p1, p2, p3, p4, p5,
p16, p17, p18, p19, p20, p21, p22, p23,
p24, p25, p26, p27, p28, p29, p30, p31,
p32, p33, p34, p35, p36, p37, p38, p39,
p40, p41, p42, p43, p44, p45, p46, p47,
p48, p49, p50, p51, p52, p53, p54, p55,
p56, p57, p58, p59, p60, p61, p62, p63
*/
];
// Our instruction set
let InstructionSet = IA64InstrInfo;

15
llvm/lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -90,6 +90,21 @@ void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
}
const unsigned* IA64RegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = {
IA64::r5, 0
};
return CalleeSaveRegs;
}
const TargetRegisterClass* const*
IA64RegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
&IA64::GRRegClass, 0
};
return CalleeSaveRegClasses;
}
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//

4
llvm/lib/Target/IA64/IA64RegisterInfo.h
View File

@ -40,6 +40,10 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const;
const unsigned *getCalleeSaveRegs() const;
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const;

9
llvm/lib/Target/PowerPC/PPC.td
View File

@ -83,13 +83,4 @@ def PPCInstrInfo : InstrInfo {
def PPC : Target {
// Information about the instructions.
let InstructionSet = PPCInstrInfo;
// According to the Mach-O Runtime ABI, these regs are nonvolatile across
// calls
let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
F30, F31, CR2, CR3, CR4, V20, V21, V22, V23, V24, V25, V26, V27, V28,
V29, V30, V31, LR];
}

67
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -182,6 +182,73 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
}
}
const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = {
PPC::R1, PPC::R13,
PPC::R14, PPC::R15,
PPC::R16, PPC::R17,
PPC::R18, PPC::R19,
PPC::R20, PPC::R21,
PPC::R22, PPC::R23,
PPC::R24, PPC::R25,
PPC::R26, PPC::R27,
PPC::R28, PPC::R29,
PPC::R30, PPC::R31,
PPC::F14, PPC::F15,
PPC::F16, PPC::F17,
PPC::F18, PPC::F19,
PPC::F20, PPC::F21,
PPC::F22, PPC::F23,
PPC::F24, PPC::F25,
PPC::F26, PPC::F27,
PPC::F28, PPC::F29,
PPC::F30, PPC::F31,
PPC::CR2, PPC::CR3,
PPC::CR4, PPC::V20,
PPC::V21, PPC::V22,
PPC::V23, PPC::V24,
PPC::V25, PPC::V26,
PPC::V27, PPC::V28,
PPC::V29, PPC::V30,
PPC::V31, PPC::LR, 0
};
return CalleeSaveRegs;
}
const TargetRegisterClass* const*
PPCRegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::GPRCRegClass, &PPC::GPRCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::F8RCRegClass, &PPC::F8RCRegClass,
&PPC::CRRCRegClass, &PPC::CRRCRegClass,
&PPC::CRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::VRRCRegClass,
&PPC::VRRCRegClass, &PPC::GPRCRegClass, 0
};
return CalleeSaveRegClasses;
}
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,

4
llvm/lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -51,6 +51,10 @@ public:
virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
int FrameIndex) const;
const unsigned *getCalleeSaveRegs() const;
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;

3
llvm/lib/Target/Sparc/Sparc.td
View File

@ -75,9 +75,6 @@ def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
//===----------------------------------------------------------------------===//
def Sparc : Target {
// FIXME: Specify callee-saved registers
let CalleeSavedRegisters = [];
// Pull in Instruction Info:
let InstructionSet = SparcInstrInfo;
}

12
llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -103,6 +103,18 @@ MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
return 0;
}
const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = { 0 };
return CalleeSaveRegs;
}
const TargetRegisterClass* const*
SparcRegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
return CalleeSaveRegClasses;
}
void SparcRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {

4
llvm/lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -46,6 +46,10 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
unsigned OpNum,
int FrameIndex) const;
const unsigned *getCalleeSaveRegs() const;
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;

3
llvm/lib/Target/X86/X86.td
View File

@ -130,9 +130,6 @@ def IntelAsmWriter : AsmWriter {
def X86 : Target {
// Specify the callee saved registers.
let CalleeSavedRegisters = [ESI, EDI, EBX, EBP];
// Information about the instructions...
let InstructionSet = X86InstrInfo;

16
llvm/lib/Target/X86/X86RegisterInfo.cpp
View File

@ -600,6 +600,22 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
return NULL;
}
const unsigned *X86RegisterInfo::getCalleeSaveRegs() const {
static const unsigned CalleeSaveRegs[] = {
X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
};
return CalleeSaveRegs;
}
const TargetRegisterClass* const*
X86RegisterInfo::getCalleeSaveRegClasses() const {
static const TargetRegisterClass * const CalleeSaveRegClasses[] = {
&X86::GR32RegClass, &X86::GR32RegClass,
&X86::GR32RegClass, &X86::GR32RegClass, 0
};
return CalleeSaveRegClasses;
}
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//

14
llvm/lib/Target/X86/X86RegisterInfo.h
View File

@ -47,10 +47,18 @@ struct X86RegisterInfo : public X86GenRegisterInfo {
/// folding and return true, otherwise it should return false. If it folds
/// the instruction, it is likely that the MachineInstruction the iterator
/// references has been changed.
virtual MachineInstr* foldMemoryOperand(MachineInstr* MI,
unsigned OpNum,
int FrameIndex) const;
MachineInstr* foldMemoryOperand(MachineInstr* MI,
unsigned OpNum,
int FrameIndex) const;
/// getCalleeSaveRegs - Return a null-terminated list of all of the
/// callee-save registers on this target.
const unsigned *getCalleeSaveRegs() const;
/// getCalleeSaveRegClasses - Return a null-terminated list of the preferred
/// register classes to spill each callee-saved register with. The order and
/// length of this list match the getCalleeSaveRegs() list.
const TargetRegisterClass* const* getCalleeSaveRegClasses() const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,