forked from OSchip/llvm-project
[AArch64] Further enable UnrollAndJam
Due to the dependency on runtime unrolling, UnJ is only enabled by default on in-order scheduling models, and if a cpu is specified through -mcpu. Differential Revision: https://reviews.llvm.org/D103604
This commit is contained in:
Nicholas Guy
parent
b5dea8701b
commit
3043cbc436
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@ -1405,6 +1405,9 @@ void AArch64TTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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UP.UpperBound = true;
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UP.UnrollRemainder = true;
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UP.DefaultUnrollRuntimeCount = 4;
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UP.UnrollAndJam = true;
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UP.UnrollAndJamInnerLoopThreshold = 60;
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}
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}
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@ -0,0 +1,95 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes='loop-unroll-and-jam' < %s -mcpu=cortex-a55 -mtriple=aarch64-none-linux-eabi -S | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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define void @unj(i32 %I, i32 %argj, i32* noalias nocapture %A, i32* noalias nocapture readonly %B) #0 {
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; CHECK-LABEL: @unj(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[ARGJ:%.*]], 0
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_END:%.*]], label [[FOR_PREHEADER:%.*]]
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; CHECK: for.preheader:
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; CHECK-NEXT: br label [[FOR_OUTER:%.*]]
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; CHECK: for.outer:
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; CHECK-NEXT: br label [[FOR_INNER:%.*]]
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; CHECK: for.inner:
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; CHECK-NEXT: [[J:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[SUM:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[J_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_1:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[SUM_1:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_1:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[J_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_2:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[SUM_2:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_2:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[J_3:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[INC_3:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[SUM_3:%.*]] = phi i32 [ 0, [[FOR_OUTER]] ], [ [[ADD_3:%.*]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[B:%.*]], i32 [[J]]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[SUB:%.*]] = add i32 [[SUM]], 10
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; CHECK-NEXT: [[ADD]] = sub i32 [[SUB]], [[TMP0]]
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; CHECK-NEXT: [[INC]] = add nuw i32 [[J]], 1
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; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 [[J_1]]
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX_1]], align 4
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; CHECK-NEXT: [[SUB_1:%.*]] = add i32 [[SUM_1]], 10
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; CHECK-NEXT: [[ADD_1]] = sub i32 [[SUB_1]], [[TMP1]]
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; CHECK-NEXT: [[INC_1]] = add nuw i32 [[J_1]], 1
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; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 [[J_2]]
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; CHECK-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX_2]], align 4
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; CHECK-NEXT: [[SUB_2:%.*]] = add i32 [[SUM_2]], 10
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; CHECK-NEXT: [[ADD_2]] = sub i32 [[SUB_2]], [[TMP2]]
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; CHECK-NEXT: [[INC_2]] = add nuw i32 [[J_2]], 1
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; CHECK-NEXT: [[ARRAYIDX_3:%.*]] = getelementptr inbounds i32, i32* [[B]], i32 [[J_3]]
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX_3]], align 4
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; CHECK-NEXT: [[SUB_3:%.*]] = add i32 [[SUM_3]], 10
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; CHECK-NEXT: [[ADD_3]] = sub i32 [[SUB_3]], [[TMP3]]
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; CHECK-NEXT: [[INC_3]] = add nuw i32 [[J_3]], 1
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; CHECK-NEXT: [[EXITCOND_3:%.*]] = icmp eq i32 [[INC_3]], [[ARGJ]]
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; CHECK-NEXT: br i1 [[EXITCOND_3]], label [[FOR_LATCH:%.*]], label [[FOR_INNER]]
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; CHECK: for.latch:
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; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[ADD_LCSSA_1:%.*]] = phi i32 [ [[ADD_1]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[ADD_LCSSA_2:%.*]] = phi i32 [ [[ADD_2]], [[FOR_INNER]] ]
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; CHECK-NEXT: [[ADD_LCSSA_3:%.*]] = phi i32 [ [[ADD_3]], [[FOR_INNER]] ]
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; CHECK-NEXT: store i32 [[ADD_LCSSA]], i32* [[A:%.*]], align 4
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; CHECK-NEXT: [[ARRAYIDX6_1:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 1
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; CHECK-NEXT: store i32 [[ADD_LCSSA_1]], i32* [[ARRAYIDX6_1]], align 4
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; CHECK-NEXT: [[ARRAYIDX6_2:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 2
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; CHECK-NEXT: store i32 [[ADD_LCSSA_2]], i32* [[ARRAYIDX6_2]], align 4
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; CHECK-NEXT: [[ARRAYIDX6_3:%.*]] = getelementptr inbounds i32, i32* [[A]], i32 3
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; CHECK-NEXT: store i32 [[ADD_LCSSA_3]], i32* [[ARRAYIDX6_3]], align 4
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; CHECK-NEXT: br label [[FOR_END_LOOPEXIT:%.*]]
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; CHECK: for.end.loopexit:
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; CHECK-NEXT: br label [[FOR_END]]
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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%cmp = icmp eq i32 %argj, 0
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br i1 %cmp, label %for.end, label %for.preheader
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for.preheader:
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br label %for.outer
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for.outer:
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%i = phi i32 [ %add8, %for.latch ], [ 0, %for.preheader ]
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br label %for.inner
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for.inner:
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%j = phi i32 [ 0, %for.outer ], [ %inc, %for.inner ]
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%sum = phi i32 [ 0, %for.outer ], [ %add, %for.inner ]
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%arrayidx = getelementptr inbounds i32, i32* %B, i32 %j
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%0 = load i32, i32* %arrayidx, align 4
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%sub = add i32 %sum, 10
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%add = sub i32 %sub, %0
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%inc = add nuw i32 %j, 1
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%exitcond = icmp eq i32 %inc, %argj
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br i1 %exitcond, label %for.latch, label %for.inner
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for.latch:
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%arrayidx6 = getelementptr inbounds i32, i32* %A, i32 %i
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store i32 %add, i32* %arrayidx6, align 4
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%add8 = add nuw nsw i32 %i, 1
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%exitcond23 = icmp eq i32 %add8, 4
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br i1 %exitcond23, label %for.end, label %for.outer
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for.end:
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ret void
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}
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