forked from OSchip/llvm-project
[CallSite removal][CodeGen] Replace ImmutableCallSite with CallBase in isInTailCallPosition.
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@ -119,7 +119,7 @@ ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
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/// between it and the return.
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///
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/// This function only tests target-independent requirements.
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bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM);
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bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM);
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/// Test if given that the input instruction is in the tail call position, if
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/// there is an attribute mismatch between the caller and the callee that will
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@ -509,9 +509,8 @@ static bool nextRealType(SmallVectorImpl<Type *> &SubTypes,
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/// between it and the return.
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///
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/// This function only tests target-independent requirements.
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bool llvm::isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM) {
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const Instruction *I = CS.getInstruction();
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const BasicBlock *ExitBB = I->getParent();
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bool llvm::isInTailCallPosition(const CallBase &Call, const TargetMachine &TM) {
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const BasicBlock *ExitBB = Call.getParent();
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const Instruction *Term = ExitBB->getTerminator();
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const ReturnInst *Ret = dyn_cast<ReturnInst>(Term);
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@ -525,15 +524,15 @@ bool llvm::isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM) {
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// been fully understood.
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if (!Ret &&
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((!TM.Options.GuaranteedTailCallOpt &&
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CS.getCallingConv() != CallingConv::Tail) || !isa<UnreachableInst>(Term)))
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Call.getCallingConv() != CallingConv::Tail) || !isa<UnreachableInst>(Term)))
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return false;
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// If I will have a chain, make sure no other instruction that will have a
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// chain interposes between I and the return.
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if (I->mayHaveSideEffects() || I->mayReadFromMemory() ||
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!isSafeToSpeculativelyExecute(I))
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if (Call.mayHaveSideEffects() || Call.mayReadFromMemory() ||
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!isSafeToSpeculativelyExecute(&Call))
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for (BasicBlock::const_iterator BBI = std::prev(ExitBB->end(), 2);; --BBI) {
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if (&*BBI == I)
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if (&*BBI == &Call)
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break;
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// Debug info intrinsics do not get in the way of tail call optimization.
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if (isa<DbgInfoIntrinsic>(BBI))
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@ -551,7 +550,7 @@ bool llvm::isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM) {
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const Function *F = ExitBB->getParent();
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return returnTypeIsEligibleForTailCall(
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F, I, Ret, *TM.getSubtargetImpl(*F)->getTargetLowering());
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F, &Call, Ret, *TM.getSubtargetImpl(*F)->getTargetLowering());
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}
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bool llvm::attributesPermitTailCall(const Function *F, const Instruction *I,
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@ -68,8 +68,7 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder, const CallBase &CB,
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Info.SwiftErrorVReg = SwiftErrorVReg;
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Info.IsMustTailCall = CB.isMustTailCall();
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Info.IsTailCall =
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CB.isTailCall() &&
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isInTailCallPosition(ImmutableCallSite(&CB), MF.getTarget()) &&
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CB.isTailCall() && isInTailCallPosition(CB, MF.getTarget()) &&
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(MF.getFunction()
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.getFnAttribute("disable-tail-calls")
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.getValueAsString() != "true");
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@ -1282,7 +1282,7 @@ bool FastISel::lowerCall(const CallInst *CI) {
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// Check if target-independent constraints permit a tail call here.
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// Target-dependent constraints are checked within fastLowerCall.
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bool IsTailCall = CI->isTailCall();
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if (IsTailCall && !isInTailCallPosition(CI, TM))
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if (IsTailCall && !isInTailCallPosition(*CI, TM))
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IsTailCall = false;
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if (IsTailCall && MF->getFunction()
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.getFnAttribute("disable-tail-calls")
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@ -5698,7 +5698,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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Align SrcAlign = MCI.getSourceAlign().valueOrOne();
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Align Alignment = commonAlignment(DstAlign, SrcAlign);
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bool isVol = MCI.isVolatile();
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bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
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bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
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// FIXME: Support passing different dest/src alignments to the memcpy DAG
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// node.
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SDValue Root = isVol ? getRoot() : getMemoryRoot();
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@ -5720,7 +5720,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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Align SrcAlign = MCI.getSourceAlign().valueOrOne();
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Align Alignment = commonAlignment(DstAlign, SrcAlign);
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bool isVol = MCI.isVolatile();
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bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
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bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
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// FIXME: Support passing different dest/src alignments to the memcpy DAG
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// node.
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SDValue MC = DAG.getMemcpy(getRoot(), sdl, Dst, Src, Size, Alignment, isVol,
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@ -5738,7 +5738,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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// @llvm.memset defines 0 and 1 to both mean no alignment.
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Align Alignment = MSI.getDestAlign().valueOrOne();
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bool isVol = MSI.isVolatile();
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bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
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bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
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SDValue Root = isVol ? getRoot() : getMemoryRoot();
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SDValue MS = DAG.getMemset(Root, sdl, Op1, Op2, Op3, Alignment, isVol, isTC,
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MachinePointerInfo(I.getArgOperand(0)));
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@ -5755,7 +5755,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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Align SrcAlign = MMI.getSourceAlign().valueOrOne();
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Align Alignment = commonAlignment(DstAlign, SrcAlign);
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bool isVol = MMI.isVolatile();
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bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
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bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
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// FIXME: Support passing different dest/src alignments to the memmove DAG
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// node.
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SDValue Root = isVol ? getRoot() : getMemoryRoot();
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@ -5775,7 +5775,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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unsigned SrcAlign = MI.getSourceAlignment();
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Type *LengthTy = MI.getLength()->getType();
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unsigned ElemSz = MI.getElementSizeInBytes();
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bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
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bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
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SDValue MC = DAG.getAtomicMemcpy(getRoot(), sdl, Dst, DstAlign, Src,
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SrcAlign, Length, LengthTy, ElemSz, isTC,
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MachinePointerInfo(MI.getRawDest()),
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@ -5793,7 +5793,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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unsigned SrcAlign = MI.getSourceAlignment();
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Type *LengthTy = MI.getLength()->getType();
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unsigned ElemSz = MI.getElementSizeInBytes();
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bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
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bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
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SDValue MC = DAG.getAtomicMemmove(getRoot(), sdl, Dst, DstAlign, Src,
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SrcAlign, Length, LengthTy, ElemSz, isTC,
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MachinePointerInfo(MI.getRawDest()),
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@ -5810,7 +5810,7 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
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unsigned DstAlign = MI.getDestAlignment();
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Type *LengthTy = MI.getLength()->getType();
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unsigned ElemSz = MI.getElementSizeInBytes();
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bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
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bool isTC = I.isTailCall() && isInTailCallPosition(I, DAG.getTarget());
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SDValue MC = DAG.getAtomicMemset(getRoot(), sdl, Dst, DstAlign, Val, Length,
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LengthTy, ElemSz, isTC,
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MachinePointerInfo(MI.getRawDest()));
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@ -7124,8 +7124,7 @@ void SelectionDAGBuilder::LowerCallTo(const CallBase &CB, SDValue Callee,
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// Check if target-independent constraints permit a tail call here.
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// Target-dependent constraints are checked within TLI->LowerCallTo.
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if (isTailCall &&
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!isInTailCallPosition(ImmutableCallSite(&CB), DAG.getTarget()))
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if (isTailCall && !isInTailCallPosition(CB, DAG.getTarget()))
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isTailCall = false;
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// Disable tail calls if there is an swifterror argument. Targets have not
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