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Switch over to MachineLoopInfo. 

llvm-svn: 44838
This commit is contained in:
Evan Cheng 2007-12-11 02:09:15 +00:00
parent f54030231e
commit 303417d242
5 changed files with 28 additions and 28 deletions
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9
llvm/include/llvm/CodeGen/LiveIntervalAnalysis.h
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@ -32,7 +32,7 @@
namespace llvm { namespace llvm {
class LiveVariables; class LiveVariables;
class LoopInfo; class MachineLoopInfo;
class MRegisterInfo; class MRegisterInfo;
class SSARegMap; class SSARegMap;
class TargetInstrInfo; class TargetInstrInfo;
@ -231,7 +231,7 @@ namespace llvm {
/// the given interval. /// the given interval.
std::vector<LiveInterval*> std::vector<LiveInterval*>
addIntervalsForSpills(const LiveInterval& i, addIntervalsForSpills(const LiveInterval& i,
const LoopInfo *loopInfo, VirtRegMap& vrm); const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
/// isReMaterializable - Returns true if every definition of MI of every /// isReMaterializable - Returns true if every definition of MI of every
/// val# of the specified interval is re-materializable. Also returns true /// val# of the specified interval is re-materializable. Also returns true
@ -321,7 +321,8 @@ namespace llvm {
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete, bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc, VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds, SmallVector<int, 4> &ReMatIds,
unsigned &NewVReg, bool &HasDef, bool &HasUse, const LoopInfo *loopInfo, unsigned &NewVReg, bool &HasDef, bool &HasUse,
const MachineLoopInfo *loopInfo,
std::map<unsigned,unsigned> &MBBVRegsMap, std::map<unsigned,unsigned> &MBBVRegsMap,
std::vector<LiveInterval*> &NewLIs); std::vector<LiveInterval*> &NewLIs);
void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit, void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
@ -329,7 +330,7 @@ namespace llvm {
MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot, MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete, bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc, VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds, const LoopInfo *loopInfo, SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
BitVector &SpillMBBs, BitVector &SpillMBBs,
std::map<unsigned,std::vector<SRInfo> > &SpillIdxes, std::map<unsigned,std::vector<SRInfo> > &SpillIdxes,
BitVector &RestoreMBBs, BitVector &RestoreMBBs,

10
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -19,10 +19,10 @@
#include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "VirtRegMap.h" #include "VirtRegMap.h"
#include "llvm/Value.h" #include "llvm/Value.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/SSARegMap.h"
#include "llvm/Target/MRegisterInfo.h" #include "llvm/Target/MRegisterInfo.h"
@ -765,7 +765,7 @@ rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
const TargetRegisterClass* rc, const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds, SmallVector<int, 4> &ReMatIds,
unsigned &NewVReg, bool &HasDef, bool &HasUse, unsigned &NewVReg, bool &HasDef, bool &HasUse,
const LoopInfo *loopInfo, const MachineLoopInfo *loopInfo,
std::map<unsigned,unsigned> &MBBVRegsMap, std::map<unsigned,unsigned> &MBBVRegsMap,
std::vector<LiveInterval*> &NewLIs) { std::vector<LiveInterval*> &NewLIs) {
bool CanFold = false; bool CanFold = false;
@ -962,7 +962,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
VirtRegMap &vrm, SSARegMap *RegMap, VirtRegMap &vrm, SSARegMap *RegMap,
const TargetRegisterClass* rc, const TargetRegisterClass* rc,
SmallVector<int, 4> &ReMatIds, SmallVector<int, 4> &ReMatIds,
const LoopInfo *loopInfo, const MachineLoopInfo *loopInfo,
BitVector &SpillMBBs, BitVector &SpillMBBs,
std::map<unsigned, std::vector<SRInfo> > &SpillIdxes, std::map<unsigned, std::vector<SRInfo> > &SpillIdxes,
BitVector &RestoreMBBs, BitVector &RestoreMBBs,
@ -1119,7 +1119,7 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
} }
// Update spill weight. // Update spill weight.
unsigned loopDepth = loopInfo->getLoopDepth(MBB->getBasicBlock()); unsigned loopDepth = loopInfo->getLoopDepth(MBB);
nI.weight += getSpillWeight(HasDef, HasUse, loopDepth); nI.weight += getSpillWeight(HasDef, HasUse, loopDepth);
} }
@ -1158,7 +1158,7 @@ void LiveIntervals::eraseRestoreInfo(int Id, int index, unsigned vr,
std::vector<LiveInterval*> LiveIntervals:: std::vector<LiveInterval*> LiveIntervals::
addIntervalsForSpills(const LiveInterval &li, addIntervalsForSpills(const LiveInterval &li,
const LoopInfo *loopInfo, VirtRegMap &vrm) { const MachineLoopInfo *loopInfo, VirtRegMap &vrm) {
// Since this is called after the analysis is done we don't know if // Since this is called after the analysis is done we don't know if
// LiveVariables is available // LiveVariables is available
lv_ = getAnalysisToUpdate<LiveVariables>(); lv_ = getAnalysisToUpdate<LiveVariables>();

8
llvm/lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -16,9 +16,9 @@
#include "PhysRegTracker.h" #include "PhysRegTracker.h"
#include "VirtRegMap.h" #include "VirtRegMap.h"
#include "llvm/Function.h" #include "llvm/Function.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/CodeGen/RegisterCoalescer.h"
@ -67,7 +67,7 @@ namespace {
SSARegMap *regmap_; SSARegMap *regmap_;
BitVector allocatableRegs_; BitVector allocatableRegs_;
LiveIntervals* li_; LiveIntervals* li_;
const LoopInfo *loopInfo; const MachineLoopInfo *loopInfo;
/// handled_ - Intervals are added to the handled_ set in the order of their /// handled_ - Intervals are added to the handled_ set in the order of their
/// start value. This is uses for backtracking. /// start value. This is uses for backtracking.
@ -103,7 +103,7 @@ namespace {
// Make sure PassManager knows which analyses to make available // Make sure PassManager knows which analyses to make available
// to coalescing and which analyses coalescing invalidates. // to coalescing and which analyses coalescing invalidates.
AU.addRequiredTransitive<RegisterCoalescer>(); AU.addRequiredTransitive<RegisterCoalescer>();
AU.addRequired<LoopInfo>(); AU.addRequired<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
@ -254,7 +254,7 @@ bool RALinScan::runOnMachineFunction(MachineFunction &fn) {
regmap_ = mf_->getSSARegMap(); regmap_ = mf_->getSSARegMap();
allocatableRegs_ = mri_->getAllocatableSet(fn); allocatableRegs_ = mri_->getAllocatableSet(fn);
li_ = &getAnalysis<LiveIntervals>(); li_ = &getAnalysis<LiveIntervals>();
loopInfo = &getAnalysis<LoopInfo>(); loopInfo = &getAnalysis<MachineLoopInfo>();
// We don't run the coalescer here because we have no reason to // We don't run the coalescer here because we have no reason to
// interact with it. If the coalescer requires interaction, it // interact with it. If the coalescer requires interaction, it

25
llvm/lib/CodeGen/SimpleRegisterCoalescing.cpp
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@ -17,10 +17,10 @@
#include "VirtRegMap.h" #include "VirtRegMap.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/Value.h" #include "llvm/Value.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/SSARegMap.h" #include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/CodeGen/RegisterCoalescer.h"
@ -72,7 +72,7 @@ void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreservedID(TwoAddressInstructionPassID); AU.addPreservedID(TwoAddressInstructionPassID);
AU.addRequired<LiveVariables>(); AU.addRequired<LiveVariables>();
AU.addRequired<LiveIntervals>(); AU.addRequired<LiveIntervals>();
AU.addRequired<LoopInfo>(); AU.addRequired<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
@ -207,11 +207,10 @@ void SimpleRegisterCoalescing::AddSubRegIdxPairs(unsigned Reg, unsigned SubIdx)
bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI, bool SimpleRegisterCoalescing::isBackEdgeCopy(MachineInstr *CopyMI,
unsigned DstReg) { unsigned DstReg) {
MachineBasicBlock *MBB = CopyMI->getParent(); MachineBasicBlock *MBB = CopyMI->getParent();
const BasicBlock *BB = MBB->getBasicBlock(); const MachineLoop *L = loopInfo->getLoopFor(MBB);
const Loop *L = loopInfo->getLoopFor(BB);
if (!L) if (!L)
return false; return false;
if (BB != L->getLoopLatch()) if (MBB != L->getLoopLatch())
return false; return false;
DstReg = rep(DstReg); DstReg = rep(DstReg);
@ -540,8 +539,7 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec TheCopy, bool &Again) {
unsigned SrcReg, DstReg; unsigned SrcReg, DstReg;
if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg) && if (CopyMI && tii_->isMoveInstr(*CopyMI, SrcReg, DstReg) &&
JoinedCopies.count(CopyMI) == 0) { JoinedCopies.count(CopyMI) == 0) {
unsigned LoopDepth = unsigned LoopDepth = loopInfo->getLoopDepth(CopyMI->getParent());
loopInfo->getLoopDepth(CopyMI->getParent()->getBasicBlock());
JoinQueue->push(CopyRec(CopyMI, SrcReg, DstReg, LoopDepth, JoinQueue->push(CopyRec(CopyMI, SrcReg, DstReg, LoopDepth,
isBackEdgeCopy(CopyMI, DstReg))); isBackEdgeCopy(CopyMI, DstReg)));
} }
@ -1072,7 +1070,7 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
std::vector<CopyRec> VirtCopies; std::vector<CopyRec> VirtCopies;
std::vector<CopyRec> PhysCopies; std::vector<CopyRec> PhysCopies;
unsigned LoopDepth = loopInfo->getLoopDepth(MBB->getBasicBlock()); unsigned LoopDepth = loopInfo->getLoopDepth(MBB);
for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end(); for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
MII != E;) { MII != E;) {
MachineInstr *Inst = MII++; MachineInstr *Inst = MII++;
@ -1143,9 +1141,10 @@ void SimpleRegisterCoalescing::joinIntervals() {
// Join intervals in the function prolog first. We want to join physical // Join intervals in the function prolog first. We want to join physical
// registers with virtual registers before the intervals got too long. // registers with virtual registers before the intervals got too long.
std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs; std::vector<std::pair<unsigned, MachineBasicBlock*> > MBBs;
for (MachineFunction::iterator I = mf_->begin(), E = mf_->end(); I != E;++I) for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();I != E;++I){
MBBs.push_back(std::make_pair(loopInfo-> MachineBasicBlock *MBB = I;
getLoopDepth(I->getBasicBlock()), I)); MBBs.push_back(std::make_pair(loopInfo->getLoopDepth(MBB), I));
}
// Sort by loop depth. // Sort by loop depth.
std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare()); std::sort(MBBs.begin(), MBBs.end(), DepthMBBCompare());
@ -1380,7 +1379,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
tii_ = tm_->getInstrInfo(); tii_ = tm_->getInstrInfo();
li_ = &getAnalysis<LiveIntervals>(); li_ = &getAnalysis<LiveIntervals>();
lv_ = &getAnalysis<LiveVariables>(); lv_ = &getAnalysis<LiveVariables>();
loopInfo = &getAnalysis<LoopInfo>(); loopInfo = &getAnalysis<MachineLoopInfo>();
DOUT << "********** SIMPLE REGISTER COALESCING **********\n" DOUT << "********** SIMPLE REGISTER COALESCING **********\n"
<< "********** Function: " << "********** Function: "
@ -1427,7 +1426,7 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end(); for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
mbbi != mbbe; ++mbbi) { mbbi != mbbe; ++mbbi) {
MachineBasicBlock* mbb = mbbi; MachineBasicBlock* mbb = mbbi;
unsigned loopDepth = loopInfo->getLoopDepth(mbb->getBasicBlock()); unsigned loopDepth = loopInfo->getLoopDepth(mbb);
for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end(); for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
mii != mie; ) { mii != mie; ) {

4
llvm/lib/CodeGen/SimpleRegisterCoalescing.h
View File

@ -28,7 +28,7 @@ namespace llvm {
class MRegisterInfo; class MRegisterInfo;
class TargetInstrInfo; class TargetInstrInfo;
class VirtRegMap; class VirtRegMap;
class LoopInfo; class MachineLoopInfo;
/// CopyRec - Representation for copy instructions in coalescer queue. /// CopyRec - Representation for copy instructions in coalescer queue.
/// ///
@ -84,7 +84,7 @@ namespace llvm {
const TargetInstrInfo* tii_; const TargetInstrInfo* tii_;
LiveIntervals *li_; LiveIntervals *li_;
LiveVariables *lv_; LiveVariables *lv_;
const LoopInfo* loopInfo; const MachineLoopInfo* loopInfo;
BitVector allocatableRegs_; BitVector allocatableRegs_;
DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_; DenseMap<const TargetRegisterClass*, BitVector> allocatableRCRegs_;