forked from OSchip/llvm-project
[RISCV] Implement pseudo instructions for load/store from a symbol address.
Summary: Those pseudo-instructions are making load/store instructions able to load/store from/to a symbol, and its always using PC-relative addressing to generating a symbol address. Reviewers: asb, apazos, rogfer01, jrtc27 Differential Revision: https://reviews.llvm.org/D50496 llvm-svn: 354430
This commit is contained in:
Kito Cheng
parent
476e1b9937
commit
303217e8b4
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@ -91,6 +91,10 @@ class RISCVAsmParser : public MCTargetAsmParser {
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// Helper to emit pseudo instruction "la" used in GOT/PC-rel addressing.
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void emitLoadAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
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// Helper to emit pseudo load/store instruction with a symbol.
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void emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
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MCStreamer &Out, bool HasTmpReg);
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/// Helper for processing MC instructions that have been successfully matched
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/// by MatchAndEmitInstruction. Modifications to the emitted instructions,
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/// like the expansion of pseudo instructions (e.g., "li"), can be performed
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@ -1105,11 +1109,22 @@ OperandMatchResultTy RISCVAsmParser::parseBareSymbol(OperandVector &Operands) {
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return MatchOperand_NoMatch;
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StringRef Identifier;
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AsmToken Tok = getLexer().getTok();
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if (getParser().parseIdentifier(Identifier))
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return MatchOperand_ParseFail;
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MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
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Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
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if (Sym->isVariable()) {
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const MCExpr *V = Sym->getVariableValue(/*SetUsed=*/false);
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if (!isa<MCSymbolRefExpr>(V)) {
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getLexer().UnLex(Tok); // Put back if it's not a bare symbol.
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return MatchOperand_NoMatch;
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}
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Res = V;
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} else
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Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
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Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
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return MatchOperand_Success;
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}
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@ -1487,6 +1502,25 @@ void RISCVAsmParser::emitLoadAddress(MCInst &Inst, SMLoc IDLoc,
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emitAuipcInstPair(DestReg, DestReg, Symbol, VKHi, SecondOpcode, IDLoc, Out);
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}
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void RISCVAsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode,
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SMLoc IDLoc, MCStreamer &Out,
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bool HasTmpReg) {
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// The load/store pseudo-instruction does a pc-relative load with
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// a symbol.
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//
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// The expansion looks like this
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//
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// TmpLabel: AUIPC tmp, %pcrel_hi(symbol)
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// [S|L]X rd, %pcrel_lo(TmpLabel)(tmp)
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MCOperand DestReg = Inst.getOperand(0);
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unsigned SymbolOpIdx = HasTmpReg ? 2 : 1;
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unsigned TmpRegOpIdx = HasTmpReg ? 1 : 0;
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MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx);
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const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr();
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emitAuipcInstPair(DestReg, TmpReg, Symbol, RISCVMCExpr::VK_RISCV_PCREL_HI,
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Opcode, IDLoc, Out);
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}
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bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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MCStreamer &Out) {
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Inst.setLoc(IDLoc);
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@ -1521,6 +1555,51 @@ bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
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case RISCV::PseudoLA:
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emitLoadAddress(Inst, IDLoc, Out);
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return false;
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case RISCV::PseudoLB:
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emitLoadStoreSymbol(Inst, RISCV::LB, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLBU:
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emitLoadStoreSymbol(Inst, RISCV::LBU, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLH:
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emitLoadStoreSymbol(Inst, RISCV::LH, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLHU:
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emitLoadStoreSymbol(Inst, RISCV::LHU, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLW:
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emitLoadStoreSymbol(Inst, RISCV::LW, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLWU:
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emitLoadStoreSymbol(Inst, RISCV::LWU, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoLD:
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emitLoadStoreSymbol(Inst, RISCV::LD, IDLoc, Out, /*HasTmpReg=*/false);
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return false;
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case RISCV::PseudoFLW:
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emitLoadStoreSymbol(Inst, RISCV::FLW, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoFLD:
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emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoSB:
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emitLoadStoreSymbol(Inst, RISCV::SB, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoSH:
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emitLoadStoreSymbol(Inst, RISCV::SH, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoSW:
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emitLoadStoreSymbol(Inst, RISCV::SW, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoSD:
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emitLoadStoreSymbol(Inst, RISCV::SD, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoFSW:
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emitLoadStoreSymbol(Inst, RISCV::FSW, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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case RISCV::PseudoFSD:
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emitLoadStoreSymbol(Inst, RISCV::FSD, IDLoc, Out, /*HasTmpReg=*/true);
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return false;
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}
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emitToStreamer(Out, Inst);
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@ -108,6 +108,35 @@ class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string
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let isCodeGenOnly = 1;
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}
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// Pseudo load instructions.
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class PseudoLoad<string opcodestr, RegisterClass rdty = GPR>
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: Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
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let hasSideEffects = 0;
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let mayLoad = 1;
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let mayStore = 0;
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let isCodeGenOnly = 0;
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let isAsmParserOnly = 1;
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}
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class PseudoFloatLoad<string opcodestr, RegisterClass rdty = GPR>
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: Pseudo<(outs rdty:$rd, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> {
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let hasSideEffects = 0;
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let mayLoad = 1;
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let mayStore = 0;
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let isCodeGenOnly = 0;
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let isAsmParserOnly = 1;
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}
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// Pseudo store instructions.
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class PseudoStore<string opcodestr, RegisterClass rsty = GPR>
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: Pseudo<(outs rsty:$rs, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> {
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let hasSideEffects = 0;
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let mayLoad = 0;
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let mayStore = 1;
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let isCodeGenOnly = 0;
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let isAsmParserOnly = 1;
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}
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// Instruction formats are listed in the order they appear in the RISC-V
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// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4,
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// RVInstRAtomic) sorted alphabetically.
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@ -10,8 +10,6 @@
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//
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//===----------------------------------------------------------------------===//
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include "RISCVInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// RISC-V specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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@ -240,6 +238,12 @@ def HI20 : SDNodeXForm<imm, [{
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SDLoc(N), N->getValueType(0));
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}]>;
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//===----------------------------------------------------------------------===//
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// Instruction Formats
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//===----------------------------------------------------------------------===//
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include "RISCVInstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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@ -497,11 +501,6 @@ def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
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// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
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//===----------------------------------------------------------------------===//
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// TODO lb lh lw
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// TODO RV64I: ld
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// TODO sb sh sw
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// TODO RV64I: sd
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def : InstAlias<"nop", (ADDI X0, X0, 0)>;
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// Note that the size is 32 because up to 8 32-bit instructions are needed to
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@ -513,6 +512,22 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 32,
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def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm_li:$imm), [],
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"li", "$rd, $imm">;
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def PseudoLB : PseudoLoad<"lb">;
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def PseudoLBU : PseudoLoad<"lbu">;
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def PseudoLH : PseudoLoad<"lh">;
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def PseudoLHU : PseudoLoad<"lhu">;
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def PseudoLW : PseudoLoad<"lw">;
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def PseudoSB : PseudoStore<"sb">;
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def PseudoSH : PseudoStore<"sh">;
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def PseudoSW : PseudoStore<"sw">;
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let Predicates = [IsRV64] in {
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def PseudoLWU : PseudoLoad<"lwu">;
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def PseudoLD : PseudoLoad<"ld">;
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def PseudoSD : PseudoStore<"sd">;
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} // Predicates = [IsRV64]
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def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>;
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def : InstAlias<"not $rd, $rs", (XORI GPR:$rd, GPR:$rs, -1)>;
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def : InstAlias<"neg $rd, $rs", (SUB GPR:$rd, X0, GPR:$rs)>;
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@ -178,9 +178,6 @@ def FMV_D_X : FPUnaryOp_r<0b1111001, 0b000, FPR64, GPR, "fmv.d.x"> {
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtD] in {
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// TODO fld
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// TODO fsd
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def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
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def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
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def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
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@ -191,6 +188,9 @@ def : InstAlias<"fgt.d $rd, $rs, $rt",
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(FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
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def : InstAlias<"fge.d $rd, $rs, $rt",
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(FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
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def PseudoFLD : PseudoFloatLoad<"fld", FPR64>;
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def PseudoFSD : PseudoStore<"fsd", FPR64>;
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} // Predicates = [HasStdExtD]
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//===----------------------------------------------------------------------===//
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@ -206,9 +206,6 @@ def : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>;
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtF] in {
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// TODO flw
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// TODO fsw
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def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
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def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
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def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
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@ -244,6 +241,9 @@ def : InstAlias<"fsflagsi $imm", (CSRRWI X0, 0x001, uimm5:$imm), 2>;
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// spellings should be supported by standard tools.
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def : MnemonicAlias<"fmv.s.x", "fmv.w.x">;
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def : MnemonicAlias<"fmv.x.s", "fmv.x.w">;
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def PseudoFLW : PseudoFloatLoad<"flw", FPR32>;
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def PseudoFSW : PseudoStore<"fsw", FPR32>;
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} // Predicates = [HasStdExtF]
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//===----------------------------------------------------------------------===//
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@ -6,8 +6,8 @@ fld ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with
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fsd ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
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# Memory operand not formatted correctly
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fld ft1, a0, -200 # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
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fsd ft2, a1, 100 # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
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fld ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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fsd ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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# Invalid register names
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fld ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
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@ -6,8 +6,8 @@ flw ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with
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fsw ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
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# Memory operand not formatted correctly
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flw ft1, a0, -200 # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
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fsw ft2, a1, 100 # CHECK: :[[@LINE]]:10: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
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flw ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
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# Invalid register names
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flw ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
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@ -158,7 +158,7 @@ add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for inst
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sltiu s2, s3, 0x50, 0x60 # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
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# Memory operand not formatted correctly
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lw a4, a5, 111 # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
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lw a4, a5, 111 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
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# Too few operands
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ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -0,0 +1,16 @@
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# RUN: llvm-mc %s -triple=riscv64 | FileCheck %s
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# CHECK: .Lpcrel_hi0:
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# CHECK: auipc a2, %pcrel_hi(a_symbol)
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# CHECK: lwu a2, %pcrel_lo(.Lpcrel_hi0)(a2)
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lwu a2, a_symbol
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# CHECK: .Lpcrel_hi1:
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# CHECK: auipc a3, %pcrel_hi(a_symbol)
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# CHECK: ld a3, %pcrel_lo(.Lpcrel_hi1)(a3)
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ld a3, a_symbol
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# CHECK: .Lpcrel_hi2:
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# CHECK: auipc a4, %pcrel_hi(a_symbol)
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# CHECK: sd a3, %pcrel_lo(.Lpcrel_hi2)(a4)
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sd a3, a_symbol, a4
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@ -0,0 +1,12 @@
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+d | FileCheck %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+d | FileCheck %s
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# CHECK: .Lpcrel_hi0:
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# CHECK: auipc a2, %pcrel_hi(a_symbol)
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# CHECK: fld fa2, %pcrel_lo(.Lpcrel_hi0)(a2)
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fld fa2, a_symbol, a2
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# CHECK: .Lpcrel_hi1:
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# CHECK: auipc a3, %pcrel_hi(a_symbol)
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# CHECK: fsd fa2, %pcrel_lo(.Lpcrel_hi1)(a3)
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fsd fa2, a_symbol, a3
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@ -0,0 +1,12 @@
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+f | FileCheck %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+f | FileCheck %s
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# CHECK: .Lpcrel_hi0:
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# CHECK: auipc a2, %pcrel_hi(a_symbol)
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# CHECK: flw fa2, %pcrel_lo(.Lpcrel_hi0)(a2)
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flw fa2, a_symbol, a2
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# CHECK: .Lpcrel_hi1:
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# CHECK: auipc a3, %pcrel_hi(a_symbol)
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# CHECK: fsw fa2, %pcrel_lo(.Lpcrel_hi1)(a3)
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fsw fa2, a_symbol, a3
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@ -20,3 +20,10 @@ la x1, %hi(1234) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol nam
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la x1, %lo(1234) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
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la x1, %hi(foo) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
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la x1, %lo(foo) # CHECK: :[[@LINE]]:8: error: operand must be a bare symbol name
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sw a2, %hi(a_symbol), a3 # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
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sw a2, %lo(a_symbol), a3 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
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sw a2, %lo(a_symbol)(a4), a3 # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
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# Too few operands must be rejected
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sw a2, a_symbol # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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@ -71,3 +71,49 @@ la a3, ra
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# CHECK-PIC-RV32: lw a4, %pcrel_lo(.Lpcrel_hi9)(a4)
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# CHECK-PIC-RV64: ld a4, %pcrel_lo(.Lpcrel_hi9)(a4)
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la a4, f1
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# CHECK: .Lpcrel_hi10:
|
||||
# CHECK: auipc a0, %pcrel_hi(a_symbol)
|
||||
# CHECK: lb a0, %pcrel_lo(.Lpcrel_hi10)(a0)
|
||||
lb a0, a_symbol
|
||||
|
||||
# CHECK: .Lpcrel_hi11:
|
||||
# CHECK: auipc a1, %pcrel_hi(a_symbol)
|
||||
# CHECK: lh a1, %pcrel_lo(.Lpcrel_hi11)(a1)
|
||||
lh a1, a_symbol
|
||||
|
||||
# CHECK: .Lpcrel_hi12:
|
||||
# CHECK: auipc a2, %pcrel_hi(a_symbol)
|
||||
# CHECK: lhu a2, %pcrel_lo(.Lpcrel_hi12)(a2)
|
||||
lhu a2, a_symbol
|
||||
|
||||
# CHECK: .Lpcrel_hi13:
|
||||
# CHECK: auipc a3, %pcrel_hi(a_symbol)
|
||||
# CHECK: lw a3, %pcrel_lo(.Lpcrel_hi13)(a3)
|
||||
lw a3, a_symbol
|
||||
|
||||
# CHECK: .Lpcrel_hi14:
|
||||
# CHECK: auipc a4, %pcrel_hi(a_symbol)
|
||||
# CHECK: sb a3, %pcrel_lo(.Lpcrel_hi14)(a4)
|
||||
sb a3, a_symbol, a4
|
||||
|
||||
# CHECK: .Lpcrel_hi15:
|
||||
# CHECK: auipc a4, %pcrel_hi(a_symbol)
|
||||
# CHECK: sh a3, %pcrel_lo(.Lpcrel_hi15)(a4)
|
||||
sh a3, a_symbol, a4
|
||||
|
||||
# CHECK: .Lpcrel_hi16:
|
||||
# CHECK: auipc a4, %pcrel_hi(a_symbol)
|
||||
# CHECK: sw a3, %pcrel_lo(.Lpcrel_hi16)(a4)
|
||||
sw a3, a_symbol, a4
|
||||
|
||||
# Check that we can load the address of symbols that are spelled like a register
|
||||
# CHECK: .Lpcrel_hi17:
|
||||
# CHECK: auipc a2, %pcrel_hi(zero)
|
||||
# CHECK: lw a2, %pcrel_lo(.Lpcrel_hi17)(a2)
|
||||
lw a2, zero
|
||||
|
||||
# CHECK: .Lpcrel_hi18:
|
||||
# CHECK: auipc a4, %pcrel_hi(zero)
|
||||
# CHECK: sw a3, %pcrel_lo(.Lpcrel_hi18)(a4)
|
||||
sw a3, zero, a4
|
||||
|
|
|
|||
Loading…
Reference in New Issue