forked from OSchip/llvm-project
[AMDGPU] Assembler: basic support for SDWA instructions
Support for SDWA instructions for VOP1 and VOP2 encoding. Not done yet: - converters for support optional operands and modifiers - VOPC - sext() modifier - intrinsics - VOP2b (see vop_dpp.s) - V_MAC_F32 (see vop_dpp.s) Differential Revision: http://reviews.llvm.org/D19360 llvm-svn: 267553
This commit is contained in:
Sam Kolton
parent
323ab3975b
commit
3025e7f25f
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@ -74,6 +74,8 @@ public:
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ImmTyDppRowMask,
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ImmTyDppBankMask,
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ImmTyDppBoundCtrl,
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ImmTySdwaSel,
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ImmTySdwaDstUnused,
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ImmTyDMask,
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ImmTyUNorm,
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ImmTyDA,
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@ -253,6 +255,14 @@ public:
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return isImmTy(ImmTyDppBoundCtrl);
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}
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bool isSDWASel() const {
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return isImmTy(ImmTySdwaSel);
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}
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bool isSDWADstUnused() const {
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return isImmTy(ImmTySdwaDstUnused);
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}
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void setModifiers(unsigned Mods) {
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assert(isReg() || (isImm() && Imm.Modifiers == 0));
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if (isReg())
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@ -522,6 +532,7 @@ public:
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OperandMatchResultTy parseOptionalOps(
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const ArrayRef<OptionalOperand> &OptionalOps,
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OperandVector &Operands);
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OperandMatchResultTy parseStringWithPrefix(const char *Prefix, StringRef &Value);
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void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
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@ -569,6 +580,9 @@ public:
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void cvtDPP_mod(MCInst &Inst, const OperandVector &Operands);
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void cvtDPP_nomod(MCInst &Inst, const OperandVector &Operands);
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void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool HasMods);
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OperandMatchResultTy parseSDWASel(OperandVector &Operands);
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OperandMatchResultTy parseSDWADstUnused(OperandVector &Operands);
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};
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struct OptionalOperand {
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@ -1396,6 +1410,30 @@ AMDGPUAsmParser::parseOptionalOps(const ArrayRef<OptionalOperand> &OptionalOps,
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return MatchOperand_NoMatch;
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseStringWithPrefix(const char *Prefix, StringRef &Value) {
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if (getLexer().isNot(AsmToken::Identifier)) {
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return MatchOperand_NoMatch;
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}
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StringRef Tok = Parser.getTok().getString();
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if (Tok != Prefix) {
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return MatchOperand_NoMatch;
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}
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Parser.Lex();
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if (getLexer().isNot(AsmToken::Colon)) {
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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if (getLexer().isNot(AsmToken::Identifier)) {
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return MatchOperand_ParseFail;
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}
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Value = Parser.getTok().getString();
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return MatchOperand_Success;
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}
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//===----------------------------------------------------------------------===//
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// ds
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//===----------------------------------------------------------------------===//
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@ -2296,6 +2334,80 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands,
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
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}
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//===----------------------------------------------------------------------===//
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// sdwa
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//===----------------------------------------------------------------------===//
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseSDWASel(OperandVector &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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StringRef Value;
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AMDGPUAsmParser::OperandMatchResultTy res;
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res = parseStringWithPrefix("dst_sel", Value);
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if (res == MatchOperand_ParseFail) {
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return MatchOperand_ParseFail;
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} else if (res == MatchOperand_NoMatch) {
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res = parseStringWithPrefix("src0_sel", Value);
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if (res == MatchOperand_ParseFail) {
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return MatchOperand_ParseFail;
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} else if (res == MatchOperand_NoMatch) {
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res = parseStringWithPrefix("src1_sel", Value);
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if (res != MatchOperand_Success) {
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return res;
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}
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}
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}
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int64_t Int;
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Int = StringSwitch<int64_t>(Value)
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.Case("BYTE_0", 0)
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.Case("BYTE_1", 1)
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.Case("BYTE_2", 2)
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.Case("BYTE_3", 3)
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.Case("WORD_0", 4)
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.Case("WORD_1", 5)
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.Case("DWORD", 6)
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.Default(0xffffffff);
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Parser.Lex(); // eat last token
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if (Int == 0xffffffff) {
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return MatchOperand_ParseFail;
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}
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Operands.push_back(AMDGPUOperand::CreateImm(Int, S,
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AMDGPUOperand::ImmTySdwaSel));
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return MatchOperand_Success;
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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StringRef Value;
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AMDGPUAsmParser::OperandMatchResultTy res;
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res = parseStringWithPrefix("dst_unused", Value);
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if (res != MatchOperand_Success) {
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return res;
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}
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int64_t Int;
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Int = StringSwitch<int64_t>(Value)
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.Case("UNUSED_PAD", 0)
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.Case("UNUSED_SEXT", 1)
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.Case("UNUSED_PRESERVE", 2)
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.Default(0xffffffff);
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Parser.Lex(); // eat last token
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if (Int == 0xffffffff) {
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return MatchOperand_ParseFail;
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}
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Operands.push_back(AMDGPUOperand::CreateImm(Int, S,
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AMDGPUOperand::ImmTySdwaDstUnused));
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return MatchOperand_Success;
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}
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/// Force static initialization.
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extern "C" void LLVMInitializeAMDGPUAsmParser() {
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@ -282,6 +282,8 @@ void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
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O << "_e64 ";
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else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
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O << "_dpp ";
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else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
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O << "_sdwa ";
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else
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O << "_e32 ";
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@ -479,6 +481,51 @@ void AMDGPUInstPrinter::printBoundCtrlOperand(const MCInst *MI, unsigned OpNo,
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}
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}
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void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNo).getImm();
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switch (Imm) {
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case 0: O << "BYTE_0"; break;
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case 1: O << "BYTE_1"; break;
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case 2: O << "BYTE_2"; break;
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case 3: O << "BYTE_3"; break;
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case 4: O << "WORD_0"; break;
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case 5: O << "WORD_1"; break;
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case 6: O << "DWORD"; break;
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default: llvm_unreachable("Invalid SDWA data select operand");
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}
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}
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void AMDGPUInstPrinter::printSDWADstSel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << "dst_sel:";
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printSDWASel(MI, OpNo, O);
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}
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void AMDGPUInstPrinter::printSDWASrc0Sel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << "src0_sel:";
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printSDWASel(MI, OpNo, O);
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}
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void AMDGPUInstPrinter::printSDWASrc1Sel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << "src1_sel:";
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printSDWASel(MI, OpNo, O);
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}
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void AMDGPUInstPrinter::printSDWADstUnused(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << "dst_unused:";
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unsigned Imm = MI->getOperand(OpNo).getImm();
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switch (Imm) {
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case 0: O << "UNUSED_PAD"; break;
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case 1: O << "UNUSED_SEXT"; break;
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case 2: O << "UNUSED_PRESERVE"; break;
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default: llvm_unreachable("Invalid SDWA dest_unused operand");
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}
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}
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void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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unsigned Imm = MI->getOperand(OpNum).getImm();
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@ -67,6 +67,11 @@ private:
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void printRowMaskOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printBankMaskOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printBoundCtrlOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printSDWADstSel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printSDWASrc0Sel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printSDWASrc1Sel(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printSDWADstUnused(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
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void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
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@ -29,17 +29,18 @@ enum {
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VOP2 = 1 << 11,
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VOP3 = 1 << 12,
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VOPC = 1 << 13,
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DPP = 1 << 14,
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SDWA = 1 << 14,
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DPP = 1 << 15,
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MUBUF = 1 << 15,
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MTBUF = 1 << 16,
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SMRD = 1 << 17,
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DS = 1 << 18,
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MIMG = 1 << 19,
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FLAT = 1 << 20,
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WQM = 1 << 21,
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VGPRSpill = 1 << 22,
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VOPAsmPrefer32Bit = 1 << 23
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MUBUF = 1 << 16,
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MTBUF = 1 << 17,
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SMRD = 1 << 18,
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DS = 1 << 19,
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MIMG = 1 << 20,
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FLAT = 1 << 21,
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WQM = 1 << 22,
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VGPRSpill = 1 << 23,
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VOPAsmPrefer32Bit = 1 << 24
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};
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}
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@ -31,6 +31,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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field bits<1> VOP2 = 0;
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field bits<1> VOP3 = 0;
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field bits<1> VOPC = 0;
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field bits<1> SDWA = 0;
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field bits<1> DPP = 0;
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field bits<1> MUBUF = 0;
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@ -64,17 +65,18 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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let TSFlags{11} = VOP2;
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let TSFlags{12} = VOP3;
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let TSFlags{13} = VOPC;
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let TSFlags{14} = DPP;
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let TSFlags{14} = SDWA;
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let TSFlags{15} = DPP;
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let TSFlags{15} = MUBUF;
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let TSFlags{16} = MTBUF;
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let TSFlags{17} = SMRD;
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let TSFlags{18} = DS;
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let TSFlags{19} = MIMG;
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let TSFlags{20} = FLAT;
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let TSFlags{21} = WQM;
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let TSFlags{22} = VGPRSpill;
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let TSFlags{23} = VOPAsmPrefer32Bit;
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let TSFlags{16} = MUBUF;
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let TSFlags{17} = MTBUF;
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let TSFlags{18} = SMRD;
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let TSFlags{19} = DS;
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let TSFlags{20} = MIMG;
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let TSFlags{21} = FLAT;
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let TSFlags{22} = WQM;
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let TSFlags{23} = VGPRSpill;
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let TSFlags{24} = VOPAsmPrefer32Bit;
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let SchedRW = [Write32Bit];
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@ -576,6 +576,22 @@ class DPPOptionalMatchClass <string OpName>: AsmOperandClass {
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let IsOptional = 1;
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}
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def SDWASelMatchClass : AsmOperandClass {
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let Name = "SDWASel";
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let PredicateMethod = "isSDWASel";
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let ParserMethod = "parseSDWASel";
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let RenderMethod = "addImmOperands";
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let IsOptional = 1;
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}
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def SDWADstUnusedMatchClass : AsmOperandClass {
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let Name = "SDWADstUnused";
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let PredicateMethod = "isSDWADstUnused";
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let ParserMethod = "parseSDWADstUnused";
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let RenderMethod = "addImmOperands";
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let IsOptional = 1;
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}
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class OptionalImmAsmOperand <string OpName> : AsmOperandClass {
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let Name = "Imm"#OpName;
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let PredicateMethod = "isImm";
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@ -737,11 +753,31 @@ def bound_ctrl : Operand <i1> {
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let ParserMatchClass = DPPOptionalMatchClass<"BoundCtrl">;
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}
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def dst_sel : Operand <i32> {
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let PrintMethod = "printSDWADstSel";
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let ParserMatchClass = SDWASelMatchClass;
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}
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def src0_sel : Operand <i32> {
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let PrintMethod = "printSDWASrc0Sel";
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let ParserMatchClass = SDWASelMatchClass;
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}
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def src1_sel : Operand <i32> {
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let PrintMethod = "printSDWASrc1Sel";
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let ParserMatchClass = SDWASelMatchClass;
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}
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def hwreg : Operand <i16> {
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let PrintMethod = "printHwreg";
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let ParserMatchClass = HwregMatchClass;
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}
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def dst_unused : Operand <i32> {
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let PrintMethod = "printSDWADstUnused";
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let ParserMatchClass = SDWADstUnusedMatchClass;
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}
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} // End OperandType = "OPERAND_IMMEDIATE"
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@ -1316,16 +1352,11 @@ class getVOPSrc0ForVT<ValueType VT> {
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RegisterOperand ret = !if(!eq(VT.Size, 64), VSrc_64, VSrc_32);
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}
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// Returns the register class to use for source 1 of VOP[12C] for the
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// given VT.
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class getVOPSrc1ForVT<ValueType VT> {
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// Returns the vreg register class to use for source operand given VT
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class getVregSrcForVT<ValueType VT> {
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RegisterClass ret = !if(!eq(VT.Size, 64), VReg_64, VGPR_32);
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}
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// Returns the register class to use for DPP source operands.
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class getDPPSrcForVT<ValueType VT> {
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RegisterClass ret = !if(!eq(VT.Size, 64), VReg_64, VGPR_32);
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}
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// Returns the register class to use for sources of VOP3 instructions for the
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// given VT.
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@ -1431,7 +1462,40 @@ class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
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/* endif */)));
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}
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class getOutsDPP <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> {
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class getInsSDWA <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
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bit HasModifiers> {
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dag ret = !if (!eq(NumSrcArgs, 0),
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// VOP1 without input operands (V_NOP)
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(ins),
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!if (!eq(NumSrcArgs, 1),
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!if (!eq(HasModifiers, 1),
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// VOP1_SDWA with modifiers
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(ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
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ClampMod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
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src0_sel:$src0_sel)
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/* else */,
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// VOP1_SDWA without modifiers
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(ins Src0RC:$src0, dst_sel:$dst_sel, dst_unused:$dst_unused,
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src0_sel:$src0_sel)
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/* endif */)
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/* NumSrcArgs == 2 */,
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!if (!eq(HasModifiers, 1),
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// VOP2_SDWA with modifiers
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(ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0,
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InputModsNoDefault:$src1_modifiers, Src1RC:$src1,
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ClampMod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
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src0_sel:$src0_sel, src1_sel:$src1_sel)
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/* else */,
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// VOP2_DPP without modifiers
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(ins Src0RC:$src0, Src1RC:$src1,
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dst_sel:$dst_sel, dst_unused:$dst_unused,
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src0_sel:$src0_sel, src1_sel:$src1_sel)
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/* endif */)));
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}
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// Outs for DPP and SDWA
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class getOutsExt <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> {
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dag ret = !if(HasDst,
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!if(!eq(DstVT.Size, 1),
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(outs DstRCDPP:$sdst), // sdst for VOPC
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@ -1484,20 +1548,41 @@ class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT =
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string ret = dst#args#" $dpp_ctrl $row_mask $bank_mask $bound_ctrl";
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}
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class getHasDPP <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
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class getAsmSDWA <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
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string dst = !if(HasDst,
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!if(!eq(DstVT.Size, 1),
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"$sdst",
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"$vdst"),
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""); // use $sdst for VOPC
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string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
|
||||
string src1 = !if(!eq(NumSrcArgs, 1), "",
|
||||
!if(!eq(NumSrcArgs, 2), " $src1_modifiers",
|
||||
" $src1_modifiers,"));
|
||||
string args = !if(!eq(HasModifiers, 0),
|
||||
getAsm32<0, NumSrcArgs, DstVT>.ret,
|
||||
", "#src0#src1#", $clamp");
|
||||
string sdwa = !if(!eq(NumSrcArgs, 0),
|
||||
"",
|
||||
!if(!eq(NumSrcArgs, 1),
|
||||
" $dst_sel $dst_unused $src0_sel",
|
||||
" $dst_sel $dst_unused $src0_sel $src1_sel"
|
||||
)
|
||||
);
|
||||
string ret = dst#args#sdwa;
|
||||
}
|
||||
|
||||
// Function that checks if instruction supports DPP and SDWA
|
||||
class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
|
||||
ValueType Src1VT = i32> {
|
||||
bit ret = !if(!eq(NumSrcArgs, 3),
|
||||
0, // NumSrcArgs == 3 - No DPP for VOP3
|
||||
!if(!eq(DstVT.Size, 1),
|
||||
0, // No DPP for VOPC
|
||||
!if(!eq(DstVT.Size, 64),
|
||||
0, // 64-bit dst - No DPP for 64-bit operands
|
||||
0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
|
||||
!if(!eq(DstVT.Size, 64),
|
||||
0, // 64-bit dst - No DPP or SDWA for 64-bit operands
|
||||
!if(!eq(Src0VT.Size, 64),
|
||||
0, // 64-bit src0
|
||||
!if(!eq(Src0VT.Size, 64),
|
||||
0, // 64-bit src0
|
||||
!if(!eq(Src0VT.Size, 64),
|
||||
0, // 64-bit src2
|
||||
1
|
||||
)
|
||||
0, // 64-bit src2
|
||||
1
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1514,41 +1599,47 @@ class VOPProfile <list<ValueType> _ArgVT> {
|
|||
field ValueType Src2VT = ArgVT[3];
|
||||
field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
|
||||
field RegisterOperand DstRCDPP = getVALUDstForVT<DstVT>.ret;
|
||||
field RegisterOperand DstRCSDWA = getVALUDstForVT<DstVT>.ret;
|
||||
field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
|
||||
field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret;
|
||||
field RegisterClass Src1RC32 = getVregSrcForVT<Src1VT>.ret;
|
||||
field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
|
||||
field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
|
||||
field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
|
||||
field RegisterClass Src0DPP = getDPPSrcForVT<Src0VT>.ret;
|
||||
field RegisterClass Src1DPP = getDPPSrcForVT<Src1VT>.ret;
|
||||
|
||||
field RegisterClass Src0DPP = getVregSrcForVT<Src0VT>.ret;
|
||||
field RegisterClass Src1DPP = getVregSrcForVT<Src1VT>.ret;
|
||||
field RegisterClass Src0SDWA = getVregSrcForVT<Src0VT>.ret;
|
||||
field RegisterClass Src1SDWA = getVregSrcForVT<Src1VT>.ret;
|
||||
|
||||
field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
|
||||
field bit HasDst32 = HasDst;
|
||||
field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
|
||||
field bit HasModifiers = hasModifiers<Src0VT>.ret;
|
||||
|
||||
field bit HasDPP = getHasDPP<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
|
||||
|
||||
field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
|
||||
|
||||
field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs));
|
||||
|
||||
// VOP3b instructions are a special case with a second explicit
|
||||
// output. This is manually overridden for them.
|
||||
field dag Outs32 = Outs;
|
||||
field dag Outs64 = Outs;
|
||||
field dag OutsDPP = getOutsDPP<HasDst, DstVT, DstRCDPP>.ret;
|
||||
field dag OutsDPP = getOutsExt<HasDst, DstVT, DstRCDPP>.ret;
|
||||
field dag OutsSDWA = getOutsExt<HasDst, DstVT, DstRCDPP>.ret;
|
||||
|
||||
field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
|
||||
field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
|
||||
HasModifiers>.ret;
|
||||
field dag InsDPP = getInsDPP<Src0DPP, Src1DPP, NumSrcArgs, HasModifiers>.ret;
|
||||
field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs, HasModifiers>.ret;
|
||||
|
||||
field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
|
||||
field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
|
||||
field string AsmDPP = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
|
||||
field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
|
||||
}
|
||||
|
||||
class VOP_NO_DPP <VOPProfile p> : VOPProfile <p.ArgVT> {
|
||||
let HasDPP = 0;
|
||||
class VOP_NO_EXT <VOPProfile p> : VOPProfile <p.ArgVT> {
|
||||
let HasExt = 0;
|
||||
}
|
||||
|
||||
// FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order
|
||||
|
|
@ -1659,12 +1750,12 @@ def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
|
|||
def VOP_MADAK : VOPProfile <[f32, f32, f32, f32]> {
|
||||
field dag Ins32 = (ins VCSrc_32:$src0, VGPR_32:$src1, u32imm:$imm);
|
||||
field string Asm32 = "$vdst, $src0, $src1, $imm";
|
||||
field bit HasDPP = 0;
|
||||
field bit HasExt = 0;
|
||||
}
|
||||
def VOP_MADMK : VOPProfile <[f32, f32, f32, f32]> {
|
||||
field dag Ins32 = (ins VCSrc_32:$src0, u32imm:$imm, VGPR_32:$src1);
|
||||
field string Asm32 = "$vdst, $src0, $imm, $src1";
|
||||
field bit HasDPP = 0;
|
||||
field bit HasExt = 0;
|
||||
}
|
||||
def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
|
||||
let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
|
||||
|
|
@ -1675,9 +1766,15 @@ def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> {
|
|||
VGPR_32:$src2, // stub argument
|
||||
dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
|
||||
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
|
||||
let InsSDWA = (ins InputModsNoDefault:$src0_modifiers, Src0RC32:$src0,
|
||||
InputModsNoDefault:$src1_modifiers, Src1RC32:$src1,
|
||||
VGPR_32:$src2, // stub argument
|
||||
ClampMod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
|
||||
src0_sel:$src0_sel, src1_sel:$src1_sel);
|
||||
let Asm32 = getAsm32<1, 2, f32>.ret;
|
||||
let Asm64 = getAsm64<1, 2, HasModifiers, f32>.ret;
|
||||
let AsmDPP = getAsmDPP<1, 2, HasModifiers, f32>.ret;
|
||||
let AsmSDWA = getAsmSDWA<1, 2, HasModifiers, f32>.ret;
|
||||
}
|
||||
def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
|
||||
def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
|
||||
|
|
@ -1787,13 +1884,37 @@ multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
|
|||
class VOP1_DPP <vop1 op, string opName, VOPProfile p> :
|
||||
VOP1_DPPe <op.VI>,
|
||||
VOP_DPP <p.OutsDPP, p.InsDPP, opName#p.AsmDPP, [], p.HasModifiers> {
|
||||
let AssemblerPredicates = !if(p.HasDPP, [isVI], [DisableInst]);
|
||||
let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
|
||||
let DecoderNamespace = "DPP";
|
||||
let DisableDecoder = DisableVIDecoder;
|
||||
let src0_modifiers = !if(p.HasModifiers, ?, 0);
|
||||
let src1_modifiers = 0;
|
||||
}
|
||||
|
||||
class SDWADisableFields <VOPProfile p> {
|
||||
bits<8> src0 = !if(!eq(p.NumSrcArgs, 0), 0, ?);
|
||||
bits<3> src0_sel = !if(!eq(p.NumSrcArgs, 0), 6, ?);
|
||||
bits<3> src0_modifiers = !if(p.HasModifiers, ?, 0);
|
||||
bits<3> src1_sel = !if(!eq(p.NumSrcArgs, 0), 6,
|
||||
!if(!eq(p.NumSrcArgs, 1), 6,
|
||||
?));
|
||||
bits<3> src1_modifiers = !if(!eq(p.NumSrcArgs, 0), 0,
|
||||
!if(!eq(p.NumSrcArgs, 1), 0,
|
||||
!if(p.HasModifiers, ?, 0)));
|
||||
bits<3> dst_sel = !if(p.HasDst, ?, 6);
|
||||
bits<2> dst_unused = !if(p.HasDst, ?, 0);
|
||||
bits<1> clamp = !if(p.HasModifiers, ?, 0);
|
||||
}
|
||||
|
||||
class VOP1_SDWA <vop1 op, string opName, VOPProfile p> :
|
||||
VOP1_SDWAe <op.VI>,
|
||||
VOP_SDWA <p.OutsSDWA, p.InsSDWA, opName#p.AsmSDWA, [], p.HasModifiers>,
|
||||
SDWADisableFields <p> {
|
||||
let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
|
||||
let DecoderNamespace = "SDWA";
|
||||
let DisableDecoder = DisableVIDecoder;
|
||||
}
|
||||
|
||||
multiclass VOP1SI_m <vop1 op, string opName, VOPProfile p, list<dag> pattern,
|
||||
string asm = opName#p.Asm32> {
|
||||
|
||||
|
|
@ -1851,13 +1972,22 @@ multiclass VOP2_m <vop2 op, string opName, VOPProfile p, list <dag> pattern,
|
|||
class VOP2_DPP <vop2 op, string opName, VOPProfile p> :
|
||||
VOP2_DPPe <op.VI>,
|
||||
VOP_DPP <p.OutsDPP, p.InsDPP, opName#p.AsmDPP, [], p.HasModifiers> {
|
||||
let AssemblerPredicates = !if(p.HasDPP, [isVI], [DisableInst]);
|
||||
let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
|
||||
let DecoderNamespace = "DPP";
|
||||
let DisableDecoder = DisableVIDecoder;
|
||||
let src0_modifiers = !if(p.HasModifiers, ?, 0);
|
||||
let src1_modifiers = !if(p.HasModifiers, ?, 0);
|
||||
}
|
||||
|
||||
class VOP2_SDWA <vop2 op, string opName, VOPProfile p> :
|
||||
VOP2_SDWAe <op.VI>,
|
||||
VOP_SDWA <p.OutsSDWA, p.InsSDWA, opName#p.AsmSDWA, [], p.HasModifiers>,
|
||||
SDWADisableFields <p> {
|
||||
let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]);
|
||||
let DecoderNamespace = "SDWA";
|
||||
let DisableDecoder = DisableVIDecoder;
|
||||
}
|
||||
|
||||
class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
|
||||
|
||||
bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
|
||||
|
|
@ -2089,6 +2219,8 @@ multiclass VOP1_Helper <vop1 op, string opName, VOPProfile p, list<dag> pat32,
|
|||
p.HasModifiers>;
|
||||
|
||||
def _dpp : VOP1_DPP <op, opName, p>;
|
||||
|
||||
def _sdwa : VOP1_SDWA <op, opName, p>;
|
||||
}
|
||||
|
||||
multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
|
||||
|
|
@ -2122,6 +2254,8 @@ multiclass VOP2_Helper <vop2 op, string opName, VOPProfile p, list<dag> pat32,
|
|||
revOp, p.HasModifiers>;
|
||||
|
||||
def _dpp : VOP2_DPP <op, opName, p>;
|
||||
|
||||
def _sdwa : VOP2_SDWA <op, opName, p>;
|
||||
}
|
||||
|
||||
multiclass VOP2Inst <vop2 op, string opName, VOPProfile P,
|
||||
|
|
|
|||
|
|
@ -1394,13 +1394,13 @@ defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32",
|
|||
VOP_F32_F32, int_amdgcn_frexp_mant
|
||||
>;
|
||||
let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in {
|
||||
defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NO_DPP<VOP_NONE>>;
|
||||
defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NO_EXT<VOP_NONE>>;
|
||||
}
|
||||
|
||||
let Uses = [M0, EXEC] in {
|
||||
defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_NO_DPP<VOP_I32_I32>>;
|
||||
defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_NO_DPP<VOP_I32_I32>>;
|
||||
defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_NO_DPP<VOP_I32_I32>>;
|
||||
defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_NO_EXT<VOP_I32_I32>>;
|
||||
defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_NO_EXT<VOP_I32_I32>>;
|
||||
defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>;
|
||||
} // End Uses = [M0, EXEC]
|
||||
|
||||
// These instruction only exist on SI and CI
|
||||
|
|
|
|||
|
|
@ -225,6 +225,61 @@ class VOP2_DPPe <bits<6> op> : VOP_DPPe {
|
|||
let Inst{31} = 0x0; //encoding
|
||||
}
|
||||
|
||||
class VOP_SDWA <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> :
|
||||
VOPAnyCommon <outs, ins, asm, pattern> {
|
||||
let SDWA = 1;
|
||||
let Size = 8;
|
||||
}
|
||||
|
||||
class VOP_SDWAe : Enc64 {
|
||||
bits<8> src0;
|
||||
bits<3> src0_sel;
|
||||
bits<3> src0_modifiers; // {abs,neg,sext}
|
||||
bits<3> src1_sel;
|
||||
bits<3> src1_modifiers;
|
||||
bits<3> dst_sel;
|
||||
bits<2> dst_unused;
|
||||
bits<1> clamp;
|
||||
|
||||
let Inst{39-32} = src0;
|
||||
let Inst{42-40} = dst_sel;
|
||||
let Inst{44-43} = dst_unused;
|
||||
let Inst{45} = clamp;
|
||||
let Inst{50-48} = src0_sel;
|
||||
let Inst{53-51} = src0_modifiers;
|
||||
let Inst{58-56} = src1_sel;
|
||||
let Inst{61-59} = src1_modifiers;
|
||||
}
|
||||
|
||||
class VOP1_SDWAe <bits<8> op> : VOP_SDWAe {
|
||||
bits<8> vdst;
|
||||
|
||||
let Inst{8-0} = 0xf9; // sdwa
|
||||
let Inst{16-9} = op;
|
||||
let Inst{24-17} = vdst;
|
||||
let Inst{31-25} = 0x3f; // encoding
|
||||
}
|
||||
|
||||
class VOP2_SDWAe <bits<6> op> : VOP_SDWAe {
|
||||
bits<8> vdst;
|
||||
bits<8> src1;
|
||||
|
||||
let Inst{8-0} = 0xf9; // sdwa
|
||||
let Inst{16-9} = src1;
|
||||
let Inst{24-17} = vdst;
|
||||
let Inst{30-25} = op;
|
||||
let Inst{31} = 0x0; // encoding
|
||||
}
|
||||
|
||||
class VOPC_SDWAe <bits<8> op> : VOP_SDWAe {
|
||||
bits<8> src1;
|
||||
|
||||
let Inst{8-0} = 0xf9; // sdwa
|
||||
let Inst{16-9} = src1;
|
||||
let Inst{24-17} = op;
|
||||
let Inst{31-25} = 0x3e; // encoding
|
||||
}
|
||||
|
||||
class EXPe_vi : EXPe {
|
||||
let Inst{31-26} = 0x31; //encoding
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,40 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=GCN --check-prefix=CIVI --check-prefix=VI
|
||||
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
|
||||
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
|
||||
|
||||
// ToDo: converters
|
||||
// ToDo: VOPC
|
||||
// ToDo: VOP2b (see vop_dpp.s)
|
||||
// ToDo: V_MAC_F32 (see vop_dpp.s)
|
||||
// ToDo: sext()
|
||||
// ToDo: intrinsics
|
||||
|
||||
|
||||
// NOSICI: error:
|
||||
// VI: v_mov_b32_sdwa v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x02,0x10,0x06,0x06]
|
||||
v_mov_b32 v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
|
||||
|
||||
// NOSICI: error:
|
||||
// VI: v_mov_b32_sdwa v3, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1 ; encoding: [0xf9,0x02,0x06,0x7e,0x04,0x11,0x05,0x06]
|
||||
v_mov_b32 v3, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_1
|
||||
|
||||
// NOSICI: error:
|
||||
// VI: v_mov_b32_sdwa v15, v99 dst_sel:BYTE_2 dst_unused:UNUSED_SEXT src0_sel:WORD_0 ; encoding: [0xf9,0x02,0x1e,0x7e,0x63,0x0a,0x04,0x06]
|
||||
v_mov_b32 v15, v99 dst_sel:BYTE_2 dst_unused:UNUSED_SEXT src0_sel:WORD_0
|
||||
|
||||
// NOSICI: error:
|
||||
// VI: v_min_u32_sdwa v194, v13, v1 dst_sel:BYTE_3 dst_unused:UNUSED_SEXT src0_sel:BYTE_3 src1_sel:BYTE_2 ; encoding: [0xf9,0x02,0x84,0x1d,0x0d,0x0b,0x03,0x02]
|
||||
v_min_u32 v194, v13, v1 dst_sel:BYTE_3 dst_unused:UNUSED_SEXT src0_sel:BYTE_3 src1_sel:BYTE_2
|
||||
|
||||
// NOSICI: error:
|
||||
// VI: v_min_u32_sdwa v255, v4, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:WORD_1 ; encoding: [0xf9,0x02,0xfe,0x1d,0x04,0x04,0x02,0x05]
|
||||
v_min_u32 v255, v4, v1 dst_sel:WORD_0 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:WORD_1
|
||||
|
||||
// NOSICI: error:
|
||||
// VI: v_min_u32_sdwa v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD ; encoding: [0xf9,0x02,0x90,0x1d,0xc8,0x05,0x01,0x06]
|
||||
v_min_u32 v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
|
||||
|
||||
// NOSICI: error:
|
||||
// VI: v_min_u32_sdwa v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x1c,0x01,0x06,0x00,0x06]
|
||||
v_min_u32 v1, v1, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
||||
Loading…
Reference in New Issue