From 30247fd1d9b1129afb0213f5430ad1bb2a6c9c63 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 18 Oct 2017 00:12:43 +0000 Subject: [PATCH] [aarch64][globalisel] Register banks and classes should have distinct names. Otherwise they are ambiguous in MIR. llvm-svn: 316047 --- llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp | 7 +++---- llvm/lib/Target/AArch64/AArch64RegisterBanks.td | 2 +- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 508d3a6f24fe..391e8ed633d7 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -59,10 +59,9 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) assert(&AArch64::FPRRegBank == &RBFPR && "The order in RegBanks is messed up"); - const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID); + const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); (void)RBCCR; - assert(&AArch64::CCRRegBank == &RBCCR && - "The order in RegBanks is messed up"); + assert(&AArch64::CCRegBank == &RBCCR && "The order in RegBanks is messed up"); // The GPR register bank is fully defined by all the registers in // GR64all + its subclasses. @@ -229,7 +228,7 @@ const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass( case AArch64::XSeqPairsClassRegClassID: return getRegBank(AArch64::GPRRegBankID); case AArch64::CCRRegClassID: - return getRegBank(AArch64::CCRRegBankID); + return getRegBank(AArch64::CCRegBankID); default: llvm_unreachable("Register class not supported"); } diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBanks.td b/llvm/lib/Target/AArch64/AArch64RegisterBanks.td index c2b6c0b04e9b..eee584708f69 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterBanks.td +++ b/llvm/lib/Target/AArch64/AArch64RegisterBanks.td @@ -17,4 +17,4 @@ def GPRRegBank : RegisterBank<"GPR", [GPR64all]>; def FPRRegBank : RegisterBank<"FPR", [QQQQ]>; /// Conditional register: NZCV. -def CCRRegBank : RegisterBank<"CCR", [CCR]>; +def CCRegBank : RegisterBank<"CC", [CCR]>;