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[aarch64][globalisel] Register banks and classes should have distinct names. 

Otherwise they are ambiguous in MIR.

llvm-svn: 316047
This commit is contained in:
Daniel Sanders 2017-10-18 00:12:43 +00:00
parent 8d799f8ef9
commit 30247fd1d9
2 changed files with 4 additions and 5 deletions
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7
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
View File

@ -59,10 +59,9 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
assert(&AArch64::FPRRegBank == &RBFPR &&
"The order in RegBanks is messed up");
const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID);
(void)RBCCR;
assert(&AArch64::CCRRegBank == &RBCCR &&
"The order in RegBanks is messed up");
assert(&AArch64::CCRegBank == &RBCCR && "The order in RegBanks is messed up");
// The GPR register bank is fully defined by all the registers in
// GR64all + its subclasses.
@ -229,7 +228,7 @@ const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass(
case AArch64::XSeqPairsClassRegClassID:
return getRegBank(AArch64::GPRRegBankID);
case AArch64::CCRRegClassID:
return getRegBank(AArch64::CCRRegBankID);
return getRegBank(AArch64::CCRegBankID);
default:
llvm_unreachable("Register class not supported");
}

2
llvm/lib/Target/AArch64/AArch64RegisterBanks.td
View File

@ -17,4 +17,4 @@ def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
/// Conditional register: NZCV.
def CCRRegBank : RegisterBank<"CCR", [CCR]>;
def CCRegBank : RegisterBank<"CC", [CCR]>;