forked from OSchip/llvm-project
[X86][MC][NFC] Reduce the parameters of functions in X86MCCodeEmitter(Part II)
Summary: We determine the REX prefix used by instruction in `determineREXPrefix`, and this value is used in `emitMemModRMByte' and used as the return value of `emitOpcodePrefix`. Before this patch, REX was passed as reference to `emitPrefixImpl`, it is strange and not necessary, e.g, we have to write ``` bool Rex = false; emitPrefixImpl(CurOp, CurByte, Rex, MI, STI, OS); ``` in `emitPrefix` even if `Rex` will not be used. So we let HasREX be the return value of `emitPrefixImpl`. The HasREX is passed from `emitREXPrefix` to `emitOpcodePrefix` and then to `emitPrefixImpl`. This makes sense since REX is a kind of opcode prefix and of course is a prefix. Reviewers: craig.topper, pengfei Reviewed By: craig.topper Subscribers: annita.zhang, craig.topper, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D78276
This commit is contained in:
Shengchen Kan
parent
4bd186c0ff
commit
3017580c79
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@ -76,13 +76,12 @@ private:
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unsigned &CurByte, raw_ostream &OS) const;
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void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField,
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uint64_t TSFlags, bool Rex, unsigned &CurByte,
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uint64_t TSFlags, bool HasREX, unsigned &CurByte,
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raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void emitPrefixImpl(unsigned &CurOp, unsigned &CurByte, bool &Rex,
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const MCInst &MI, const MCSubtargetInfo &STI,
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raw_ostream &OS) const;
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bool emitPrefixImpl(unsigned &CurOp, unsigned &CurByte, const MCInst &MI,
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const MCSubtargetInfo &STI, raw_ostream &OS) const;
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void emitVEXOpcodePrefix(unsigned &CurByte, int MemOperand, const MCInst &MI,
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raw_ostream &OS) const;
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@ -93,7 +92,8 @@ private:
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bool emitOpcodePrefix(unsigned &CurByte, int MemOperand, const MCInst &MI,
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const MCSubtargetInfo &STI, raw_ostream &OS) const;
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uint8_t determineREXPrefix(const MCInst &MI, int MemOperand) const;
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bool emitREXPrefix(unsigned &CurByte, int MemOperand, const MCInst &MI,
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raw_ostream &OS) const;
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};
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} // end anonymous namespace
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@ -384,7 +384,7 @@ void X86MCCodeEmitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base,
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void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
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unsigned RegOpcodeField,
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uint64_t TSFlags, bool Rex,
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uint64_t TSFlags, bool HasREX,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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@ -412,7 +412,7 @@ void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
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default:
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return X86::reloc_riprel_4byte;
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case X86::MOV64rm:
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assert(Rex);
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assert(HasREX);
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return X86::reloc_riprel_4byte_movq_load;
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case X86::CALL64m:
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case X86::JMP64m:
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@ -426,8 +426,8 @@ void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
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case X86::SBB64rm:
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case X86::SUB64rm:
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case X86::XOR64rm:
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return Rex ? X86::reloc_riprel_4byte_relax_rex
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: X86::reloc_riprel_4byte_relax;
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return HasREX ? X86::reloc_riprel_4byte_relax_rex
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: X86::reloc_riprel_4byte_relax;
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}
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}();
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@ -649,8 +649,11 @@ void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
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CurByte, OS, Fixups);
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}
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void X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, unsigned &CurByte,
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bool &Rex, const MCInst &MI,
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/// Emit all instruction prefixes.
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///
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/// \returns true if REX prefix is used, otherwise returns false.
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bool X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, unsigned &CurByte,
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const MCInst &MI,
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const MCSubtargetInfo &STI,
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raw_ostream &OS) const {
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uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags;
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@ -696,10 +699,11 @@ void X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, unsigned &CurByte,
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// Encoding type for this instruction.
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uint64_t Encoding = TSFlags & X86II::EncodingMask;
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if (Encoding == 0)
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Rex = emitOpcodePrefix(CurByte, MemoryOperand, MI, STI, OS);
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else
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bool HasREX = false;
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if (Encoding)
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emitVEXOpcodePrefix(CurByte, MemoryOperand, MI, OS);
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else
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HasREX = emitOpcodePrefix(CurByte, MemoryOperand, MI, STI, OS);
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uint64_t Form = TSFlags & X86II::FormMask;
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switch (Form) {
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@ -748,6 +752,8 @@ void X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, unsigned &CurByte,
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break;
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}
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}
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return HasREX;
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}
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/// AVX instructions are encoded using a opcode prefix called VEX.
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@ -1181,11 +1187,14 @@ void X86MCCodeEmitter::emitVEXOpcodePrefix(unsigned &CurByte, int MemOperand,
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}
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}
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/// Determine if the MCInst has to be encoded with a X86-64 REX prefix which
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/// specifies 1) 64-bit instructions, 2) non-default operand size, and 3) use
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/// of X86-64 extended registers.
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uint8_t X86MCCodeEmitter::determineREXPrefix(const MCInst &MI,
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int MemOperand) const {
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/// Emit REX prefix which specifies
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/// 1) 64-bit instructions,
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/// 2) non-default operand size, and
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/// 3) use of X86-64 extended registers.
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///
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/// \returns true if REX prefix is used, otherwise returns false.
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bool X86MCCodeEmitter::emitREXPrefix(unsigned &CurByte, int MemOperand,
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const MCInst &MI, raw_ostream &OS) const {
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uint8_t REX = 0;
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bool UsesHighByteReg = false;
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@ -1271,7 +1280,10 @@ uint8_t X86MCCodeEmitter::determineREXPrefix(const MCInst &MI,
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report_fatal_error(
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"Cannot encode high byte register in REX-prefixed instruction");
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return REX;
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if (REX)
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emitByte(0x40 | REX, CurByte, OS);
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return REX != 0;
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}
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/// Emit segment override opcode prefix as needed.
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@ -1289,7 +1301,7 @@ void X86MCCodeEmitter::emitSegmentOverridePrefix(unsigned &CurByte,
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/// \param MemOperand the operand # of the start of a memory operand if present.
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/// If not present, it is -1.
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///
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/// \returns true if a REX prefix was used.
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/// \returns true if REX prefix is used, otherwise returns false.
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bool X86MCCodeEmitter::emitOpcodePrefix(unsigned &CurByte, int MemOperand,
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const MCInst &MI,
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const MCSubtargetInfo &STI,
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@ -1297,7 +1309,6 @@ bool X86MCCodeEmitter::emitOpcodePrefix(unsigned &CurByte, int MemOperand,
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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uint64_t TSFlags = Desc.TSFlags;
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bool Ret = false;
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// Emit the operand size opcode prefix as needed.
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if ((TSFlags & X86II::OpSizeMask) ==
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(STI.hasFeature(X86::Mode16Bit) ? X86II::OpSize32 : X86II::OpSize16))
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@ -1324,15 +1335,11 @@ bool X86MCCodeEmitter::emitOpcodePrefix(unsigned &CurByte, int MemOperand,
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}
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// Handle REX prefix.
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// FIXME: Can this come before F2 etc to simplify emission?
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if (STI.hasFeature(X86::Mode64Bit)) {
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if (uint8_t REX = determineREXPrefix(MI, MemOperand)) {
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emitByte(0x40 | REX, CurByte, OS);
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Ret = true;
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}
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} else {
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assert(!(TSFlags & X86II::REX_W) && "REX.W requires 64bit mode.");
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}
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assert((STI.hasFeature(X86::Mode64Bit) || !(TSFlags & X86II::REX_W)) &&
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"REX.W requires 64bit mode.");
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bool HasREX = STI.hasFeature(X86::Mode64Bit)
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? emitREXPrefix(CurByte, MemOperand, MI, OS)
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: false;
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// 0x0F escape code must be emitted just before the opcode.
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switch (TSFlags & X86II::OpMapMask) {
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@ -1352,7 +1359,8 @@ bool X86MCCodeEmitter::emitOpcodePrefix(unsigned &CurByte, int MemOperand,
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emitByte(0x3A, CurByte, OS);
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break;
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}
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return Ret;
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return HasREX;
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}
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void X86MCCodeEmitter::emitPrefix(const MCInst &MI, raw_ostream &OS,
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@ -1370,8 +1378,7 @@ void X86MCCodeEmitter::emitPrefix(const MCInst &MI, raw_ostream &OS,
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// Keep track of the current byte being emitted.
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unsigned CurByte = 0;
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bool Rex = false;
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emitPrefixImpl(CurOp, CurByte, Rex, MI, STI, OS);
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emitPrefixImpl(CurOp, CurByte, MI, STI, OS);
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}
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void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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@ -1391,8 +1398,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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// Keep track of the current byte being emitted.
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unsigned CurByte = 0;
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bool Rex = false;
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emitPrefixImpl(CurOp, CurByte, Rex, MI, STI, OS);
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bool HasREX = emitPrefixImpl(CurOp, CurByte, MI, STI, OS);
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// It uses the VEX.VVVV field?
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bool HasVEX_4V = TSFlags & X86II::VEX_4V;
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@ -1497,7 +1503,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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++SrcRegNum;
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emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags,
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Rex, CurByte, OS, Fixups, STI);
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HasREX, CurByte, OS, Fixups, STI);
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CurOp = SrcRegNum + 1;
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break;
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}
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@ -1570,7 +1576,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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emitByte(BaseOpcode, CurByte, OS);
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emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
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TSFlags, Rex, CurByte, OS, Fixups, STI);
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TSFlags, HasREX, CurByte, OS, Fixups, STI);
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CurOp = FirstMemOp + X86::AddrNumOperands;
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if (HasVEX_I8Reg)
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I8RegNum = getX86RegEncoding(MI, CurOp++);
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@ -1582,7 +1588,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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emitByte(BaseOpcode, CurByte, OS);
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emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
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TSFlags, Rex, CurByte, OS, Fixups, STI);
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TSFlags, HasREX, CurByte, OS, Fixups, STI);
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CurOp = FirstMemOp + X86::AddrNumOperands;
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++CurOp; // Encoded in VEX.VVVV.
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break;
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@ -1599,7 +1605,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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emitByte(BaseOpcode, CurByte, OS);
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emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)),
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TSFlags, Rex, CurByte, OS, Fixups, STI);
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TSFlags, HasREX, CurByte, OS, Fixups, STI);
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CurOp = FirstMemOp + X86::AddrNumOperands;
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break;
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}
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@ -1612,7 +1618,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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emitByte(BaseOpcode + CC, CurByte, OS);
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emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)),
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TSFlags, Rex, CurByte, OS, Fixups, STI);
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TSFlags, HasREX, CurByte, OS, Fixups, STI);
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break;
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}
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@ -1651,7 +1657,8 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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unsigned CC = MI.getOperand(CurOp++).getImm();
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emitByte(BaseOpcode + CC, CurByte, OS);
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emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Rex, CurByte, OS, Fixups, STI);
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emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, HasREX, CurByte, OS, Fixups,
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STI);
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break;
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}
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@ -1671,7 +1678,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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emitByte(BaseOpcode, CurByte, OS);
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emitMemModRMByte(MI, CurOp,
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(Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags,
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Rex, CurByte, OS, Fixups, STI);
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HasREX, CurByte, OS, Fixups, STI);
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CurOp += X86::AddrNumOperands;
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break;
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