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[DAGCombiner] Minor compile time improvement to (sext_in_reg (sign_extend_vector_inreg x)) optimization. 

Don't bother calling ComputeNumSignBits if N00Bits < ExtVTBits. No
matter what answer we get back this will be true:
(N00Bits - DAG.ComputeNumSignBits(N00, DemandedSrcElts)) < ExtVTBits)

So we might as well save the computation. This makes the code more
consistent with the similar (sext_in_reg (sext x)) handling above.
This commit is contained in:
Craig Topper 2021-03-21 10:44:31 -07:00
parent d11d5d1c5f
commit 30080b003e
1 changed files with 3 additions and 2 deletions
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5
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -11799,8 +11799,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
bool IsZext = N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG;
APInt DemandedSrcElts = APInt::getLowBitsSet(SrcElts, DstElts);
if ((N00Bits == ExtVTBits ||
(!IsZext && (N00Bits - DAG.ComputeNumSignBits(N00, DemandedSrcElts)) <
ExtVTBits)) &&
(!IsZext && (N00Bits < ExtVTBits ||
(N00Bits - DAG.ComputeNumSignBits(N00, DemandedSrcElts)) <
ExtVTBits))) &&
(!LegalOperations ||
TLI.isOperationLegal(ISD::SIGN_EXTEND_VECTOR_INREG, VT)))
return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, SDLoc(N), VT, N00);