forked from OSchip/llvm-project
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
llvm-svn: 139328
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8d9c56bb59
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2fefa427d5
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@ -77,7 +77,7 @@ public:
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EDInstInfo *getEDInfo() const;
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private:
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mutable std::vector<unsigned> ITBlock;
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void AddThumbPredicate(MCInst&) const;
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DecodeStatus AddThumbPredicate(MCInst&) const;
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void UpdateThumbVFPPredicate(MCInst&) const;
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};
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}
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@ -422,13 +422,20 @@ static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
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// encoding, but rather get their predicates from IT context. We need
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// to fix up the predicate operands using this context information as a
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// post-pass.
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void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
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MCDisassembler::DecodeStatus
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ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
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// A few instructions actually have predicates encoded in them. Don't
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// try to overwrite it if we're seeing one of those.
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switch (MI.getOpcode()) {
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case ARM::tBcc:
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case ARM::t2Bcc:
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return;
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return Success;
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case ARM::tCBZ:
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case ARM::tCBNZ:
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// Some instructions are not allowed in IT blocks.
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if (!ITBlock.empty())
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return SoftFail;
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break;
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default:
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break;
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}
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@ -456,7 +463,7 @@ void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
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MI.insert(I, MCOperand::CreateReg(0));
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else
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MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
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return;
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return Success;
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}
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}
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@ -466,6 +473,8 @@ void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
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MI.insert(I, MCOperand::CreateReg(0));
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else
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MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
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return Success;
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}
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// Thumb VFP instructions are a special case. Because we share their
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@ -516,7 +525,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 2;
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AddThumbPredicate(MI);
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Check(result, AddThumbPredicate(MI));
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return result;
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}
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@ -525,7 +534,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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if (result) {
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Size = 2;
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bool InITBlock = !ITBlock.empty();
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AddThumbPredicate(MI);
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Check(result, AddThumbPredicate(MI));
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AddThumb1SBit(MI, InITBlock);
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return result;
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}
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@ -534,7 +543,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 2;
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AddThumbPredicate(MI);
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Check(result, AddThumbPredicate(MI));
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// If we find an IT instruction, we need to parse its condition
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// code and mask operands so that we can apply them correctly
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@ -575,7 +584,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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if (result != MCDisassembler::Fail) {
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Size = 4;
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bool InITBlock = ITBlock.size();
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AddThumbPredicate(MI);
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Check(result, AddThumbPredicate(MI));
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AddThumb1SBit(MI, InITBlock);
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return result;
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}
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@ -584,7 +593,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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AddThumbPredicate(MI);
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Check(result, AddThumbPredicate(MI));
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return result;
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}
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@ -600,7 +609,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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AddThumbPredicate(MI);
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Check(result, AddThumbPredicate(MI));
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return result;
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}
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@ -612,7 +621,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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AddThumbPredicate(MI);
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Check(result, AddThumbPredicate(MI));
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return result;
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}
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}
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@ -626,7 +635,7 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
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if (result != MCDisassembler::Fail) {
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Size = 4;
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AddThumbPredicate(MI);
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Check(result, AddThumbPredicate(MI));
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return result;
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}
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}
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@ -0,0 +1,5 @@
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# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding}
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# CBZ / CBNZ not allowed in IT block.
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0xdb 0xbf 0x42 0xbb
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