forked from OSchip/llvm-project
Revert "ScheduleDAGInstrs: Rework schedule graph builder."
This works mostly fine but breaks some stage 1 builders when compiling compiler-rt on i386. Revert for further investigation as I can't see an obvious cause/fix. This reverts commit r254577. llvm-svn: 254586
This commit is contained in:
Matthias Braun
parent
311fef6ea5
commit
2fd672a221
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@ -33,26 +33,15 @@ namespace llvm {
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/// An individual mapping from virtual register number to SUnit.
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struct VReg2SUnit {
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unsigned VirtReg;
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LaneBitmask LaneMask;
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SUnit *SU;
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VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
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: VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
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VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
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unsigned getSparseSetIndex() const {
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return TargetRegisterInfo::virtReg2Index(VirtReg);
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}
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};
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/// Mapping from virtual register to SUnit including an operand index.
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struct VReg2SUnitOperIdx : public VReg2SUnit {
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unsigned OperandIndex;
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VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask,
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unsigned OperandIndex, SUnit *SU)
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: VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
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};
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/// Record a physical register access.
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/// For non-data-dependent uses, OpIdx == -1.
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struct PhysRegSUOper {
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@ -80,10 +69,7 @@ namespace llvm {
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/// Track local uses of virtual registers. These uses are gathered by the DAG
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/// builder and may be consulted by the scheduler to avoid iterating an entire
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/// vreg use list.
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typedef SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2SUnitMultiMap;
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typedef SparseMultiSet<VReg2SUnitOperIdx, VirtReg2IndexFunctor>
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VReg2SUnitOperIdxMultiMap;
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typedef SparseMultiSet<VReg2SUnit, VirtReg2IndexFunctor> VReg2UseMap;
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/// ScheduleDAGInstrs - A ScheduleDAG subclass for scheduling lists of
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/// MachineInstrs.
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@ -109,9 +95,6 @@ namespace llvm {
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/// it has taken responsibility for scheduling the terminator correctly.
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bool CanHandleTerminators;
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/// Whether lane masks should get tracked.
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bool TrackLaneMasks;
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/// State specific to the current scheduling region.
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/// ------------------------------------------------
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@ -134,7 +117,7 @@ namespace llvm {
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/// After calling BuildSchedGraph, each vreg used in the scheduling region
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/// is mapped to a set of SUnits. These include all local vreg uses, not
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/// just the uses for a singly defined vreg.
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VReg2SUnitMultiMap VRegUses;
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VReg2UseMap VRegUses;
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/// State internal to DAG building.
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/// -------------------------------
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@ -146,12 +129,8 @@ namespace llvm {
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Reg2SUnitsMap Defs;
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Reg2SUnitsMap Uses;
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/// Tracks the last instruction(s) in this region defining each virtual
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/// register. There may be multiple current definitions for a register with
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/// disjunct lanemasks.
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VReg2SUnitMultiMap CurrentVRegDefs;
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/// Tracks the last instructions in this region using each virtual register.
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VReg2SUnitOperIdxMultiMap CurrentVRegUses;
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/// Track the last instruction in this region defining each virtual register.
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VReg2SUnitMap VRegDefs;
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/// PendingLoads - Remember where unknown loads are after the most recent
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/// unknown store, as we iterate. As with Defs and Uses, this is here
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@ -221,8 +200,7 @@ namespace llvm {
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/// input.
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void buildSchedGraph(AliasAnalysis *AA,
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RegPressureTracker *RPTracker = nullptr,
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PressureDiffs *PDiffs = nullptr,
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bool TrackLaneMasks = false);
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PressureDiffs *PDiffs = nullptr);
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/// addSchedBarrierDeps - Add dependencies from instructions in the current
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/// list of instructions being scheduled to scheduling barrier. We want to
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@ -269,12 +247,6 @@ namespace llvm {
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/// Other adjustments may be made to the instruction if necessary. Return
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/// true if the operand has been deleted, false if not.
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bool toggleKillFlag(MachineInstr *MI, MachineOperand &MO);
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/// Returns a mask for which lanes get read/written by the given (register)
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/// machine operand.
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LaneBitmask getLaneMaskForMO(const MachineOperand &MO) const;
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void collectVRegUses(SUnit *SU);
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};
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/// newSUnit - Creates a new SUnit and return a ptr to it.
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@ -13,12 +13,12 @@
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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#include "llvm/ADT/IntEqClasses.h"
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#include "llvm/ADT/MapVector.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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@ -55,7 +55,7 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
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bool RemoveKillFlags)
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: ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(LIS),
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RemoveKillFlags(RemoveKillFlags), CanHandleTerminators(false),
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TrackLaneMasks(false), FirstDbgValue(nullptr) {
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FirstDbgValue(nullptr) {
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DbgValues.clear();
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const TargetSubtargetInfo &ST = mf.getSubtarget();
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@ -363,20 +363,6 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
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}
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}
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LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
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{
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unsigned Reg = MO.getReg();
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// No point in tracking lanemasks if we don't have interesting subregisters.
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const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
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if (!RC.HasDisjunctSubRegs)
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return ~0u;
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unsigned SubReg = MO.getSubReg();
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if (SubReg == 0)
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return RC.getLaneMask();
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return TRI->getSubRegIndexLaneMask(SubReg);
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}
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/// addVRegDefDeps - Add register output and data dependencies from this SUnit
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/// to instructions that occur later in the same scheduling region if they read
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/// from or write to the virtual register defined at OperIdx.
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@ -384,106 +370,35 @@ LaneBitmask ScheduleDAGInstrs::getLaneMaskForMO(const MachineOperand &MO) const
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/// TODO: Hoist loop induction variable increments. This has to be
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/// reevaluated. Generally, IV scheduling should be done before coalescing.
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void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
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MachineInstr *MI = SU->getInstr();
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MachineOperand &MO = MI->getOperand(OperIdx);
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unsigned Reg = MO.getReg();
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const MachineInstr *MI = SU->getInstr();
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unsigned Reg = MI->getOperand(OperIdx).getReg();
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LaneBitmask DefLaneMask;
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LaneBitmask KillLaneMask;
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if (TrackLaneMasks) {
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bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
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DefLaneMask = getLaneMaskForMO(MO);
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// If we have a <read-undef> flag, none of the lane values comes from an
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// earlier instruction.
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KillLaneMask = IsKill ? ~0u : DefLaneMask;
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// Clear undef flag, we'll re-add it later once we know which subregister
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// Def is first.
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MO.setIsUndef(false);
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} else {
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DefLaneMask = ~0u;
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KillLaneMask = ~0u;
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}
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if (MO.isDead()) {
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assert(CurrentVRegUses.find(Reg) == CurrentVRegUses.end() &&
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"Dead defs should have no uses");
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} else {
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// Add data dependence to all uses we found so far.
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const TargetSubtargetInfo &ST = MF.getSubtarget();
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for (VReg2SUnitOperIdxMultiMap::iterator I = CurrentVRegUses.find(Reg),
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E = CurrentVRegUses.end(); I != E; /*empty*/) {
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LaneBitmask LaneMask = I->LaneMask;
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// Ignore uses of other lanes.
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if ((LaneMask & KillLaneMask) == 0) {
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++I;
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continue;
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}
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if ((LaneMask & DefLaneMask) != 0) {
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SUnit *UseSU = I->SU;
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MachineInstr *Use = UseSU->getInstr();
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SDep Dep(SU, SDep::Data, Reg);
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Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
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I->OperandIndex));
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ST.adjustSchedDependency(SU, UseSU, Dep);
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UseSU->addPred(Dep);
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}
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LaneMask &= ~KillLaneMask;
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// If we found a Def for all lanes of this use, remove it from the list.
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if (LaneMask != 0) {
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I->LaneMask = LaneMask;
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++I;
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} else
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I = CurrentVRegUses.erase(I);
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}
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}
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// Shortcut: Singly defined vregs do not have output/anti dependencies.
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// Singly defined vregs do not have output/anti dependencies.
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// The current operand is a def, so we have at least one.
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// Check here if there are any others...
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if (MRI.hasOneDef(Reg))
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return;
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// Add output dependence to the next nearest defs of this vreg.
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// Add output dependence to the next nearest def of this vreg.
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//
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// Unless this definition is dead, the output dependence should be
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// transitively redundant with antidependencies from this definition's
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// uses. We're conservative for now until we have a way to guarantee the uses
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// are not eliminated sometime during scheduling. The output dependence edge
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// is also useful if output latency exceeds def-use latency.
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LaneBitmask LaneMask = DefLaneMask;
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for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
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CurrentVRegDefs.end())) {
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// Ignore defs for other lanes.
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if ((V2SU.LaneMask & LaneMask) == 0)
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continue;
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// Add an output dependence.
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SUnit *DefSU = V2SU.SU;
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// Ignore additional defs of the same lanes in one instruction. This can
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// happen because lanemasks are shared for targets with too many
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// subregisters. We also use some representration tricks/hacks where we
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// add super-register defs/uses, to imply that although we only access parts
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// of the reg we care about the full one.
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if (DefSU == SU)
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continue;
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SDep Dep(SU, SDep::Output, Reg);
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Dep.setLatency(
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SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
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DefSU->addPred(Dep);
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// Update current definition. This can get tricky if the def was about a
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// bigger lanemask before. We then have to shrink it and create a new
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// VReg2SUnit for the non-overlapping part.
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LaneBitmask OverlapMask = V2SU.LaneMask & LaneMask;
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LaneBitmask NonOverlapMask = V2SU.LaneMask & ~LaneMask;
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if (NonOverlapMask != 0)
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CurrentVRegDefs.insert(VReg2SUnit(Reg, NonOverlapMask, V2SU.SU));
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V2SU.SU = SU;
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V2SU.LaneMask = OverlapMask;
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VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
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if (DefI == VRegDefs.end())
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VRegDefs.insert(VReg2SUnit(Reg, SU));
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else {
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SUnit *DefSU = DefI->SU;
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if (DefSU != SU && DefSU != &ExitSU) {
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SDep Dep(SU, SDep::Output, Reg);
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Dep.setLatency(
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SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
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DefSU->addPred(Dep);
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}
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DefI->SU = SU;
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}
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// If there was no CurrentVRegDefs entry for some lanes yet, create one.
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if (LaneMask != 0)
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CurrentVRegDefs.insert(VReg2SUnit(Reg, LaneMask, SU));
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}
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/// addVRegUseDeps - Add a register data dependency if the instruction that
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@ -493,26 +408,49 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
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///
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/// TODO: Handle ExitSU "uses" properly.
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void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
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const MachineInstr *MI = SU->getInstr();
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const MachineOperand &MO = MI->getOperand(OperIdx);
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unsigned Reg = MO.getReg();
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MachineInstr *MI = SU->getInstr();
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unsigned Reg = MI->getOperand(OperIdx).getReg();
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// Remember the use. Data dependencies will be added when we find the def.
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LaneBitmask LaneMask = TrackLaneMasks ? getLaneMaskForMO(MO) : ~0u;
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CurrentVRegUses.insert(VReg2SUnitOperIdx(Reg, LaneMask, OperIdx, SU));
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// Add antidependences to the following defs of the vreg.
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for (VReg2SUnit &V2SU : make_range(CurrentVRegDefs.find(Reg),
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CurrentVRegDefs.end())) {
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// Ignore defs for unrelated lanes.
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LaneBitmask PrevDefLaneMask = V2SU.LaneMask;
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if ((PrevDefLaneMask & LaneMask) == 0)
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continue;
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if (V2SU.SU == SU)
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continue;
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V2SU.SU->addPred(SDep(SU, SDep::Anti, Reg));
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// Record this local VReg use.
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VReg2UseMap::iterator UI = VRegUses.find(Reg);
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for (; UI != VRegUses.end(); ++UI) {
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if (UI->SU == SU)
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break;
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}
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if (UI == VRegUses.end())
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VRegUses.insert(VReg2SUnit(Reg, SU));
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// Lookup this operand's reaching definition.
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assert(LIS && "vreg dependencies requires LiveIntervals");
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LiveQueryResult LRQ
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= LIS->getInterval(Reg).Query(LIS->getInstructionIndex(MI));
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VNInfo *VNI = LRQ.valueIn();
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// VNI will be valid because MachineOperand::readsReg() is checked by caller.
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assert(VNI && "No value to read by operand");
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MachineInstr *Def = LIS->getInstructionFromIndex(VNI->def);
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// Phis and other noninstructions (after coalescing) have a NULL Def.
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if (Def) {
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SUnit *DefSU = getSUnit(Def);
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if (DefSU) {
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// The reaching Def lives within this scheduling region.
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// Create a data dependence.
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SDep dep(DefSU, SDep::Data, Reg);
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// Adjust the dependence latency using operand def/use information, then
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// allow the target to perform its own adjustments.
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int DefOp = Def->findRegisterDefOperandIdx(Reg);
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dep.setLatency(SchedModel.computeOperandLatency(Def, DefOp, MI, OperIdx));
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const TargetSubtargetInfo &ST = MF.getSubtarget();
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ST.adjustSchedDependency(DefSU, SU, const_cast<SDep &>(dep));
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SU->addPred(dep);
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}
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}
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// Add antidependence to the following def of the vreg it uses.
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VReg2SUnitMap::iterator DefI = VRegDefs.find(Reg);
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if (DefI != VRegDefs.end() && DefI->SU != SU)
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DefI->SU->addPred(SDep(SU, SDep::Anti, Reg));
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}
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/// Return true if MI is an instruction we are unable to reason about
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@ -795,42 +733,17 @@ void ScheduleDAGInstrs::initSUnits() {
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}
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}
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void ScheduleDAGInstrs::collectVRegUses(SUnit *SU) {
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const MachineInstr *MI = SU->getInstr();
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for (const MachineOperand &MO : MI->operands()) {
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if (!MO.isReg())
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continue;
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if (!MO.isUse() && (MO.getSubReg() == 0 || !TrackLaneMasks))
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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// Record this local VReg use.
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VReg2SUnitMultiMap::iterator UI = VRegUses.find(Reg);
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for (; UI != VRegUses.end(); ++UI) {
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if (UI->SU == SU)
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break;
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}
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if (UI == VRegUses.end())
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VRegUses.insert(VReg2SUnit(Reg, 0, SU));
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}
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}
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/// If RegPressure is non-null, compute register pressure as a side effect. The
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/// DAG builder is an efficient place to do it because it already visits
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/// operands.
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void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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RegPressureTracker *RPTracker,
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PressureDiffs *PDiffs,
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bool TrackLaneMasks) {
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PressureDiffs *PDiffs) {
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const TargetSubtargetInfo &ST = MF.getSubtarget();
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bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
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: ST.useAA();
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AliasAnalysis *AAForDep = UseAA ? AA : nullptr;
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this->TrackLaneMasks = TrackLaneMasks;
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MISUnitMap.clear();
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ScheduleDAG::clearDAG();
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@ -864,14 +777,10 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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Defs.setUniverse(TRI->getNumRegs());
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Uses.setUniverse(TRI->getNumRegs());
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assert(CurrentVRegDefs.empty() && "nobody else should use CurrentVRegDefs");
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assert(CurrentVRegUses.empty() && "nobody else should use CurrentVRegUses");
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unsigned NumVirtRegs = MRI.getNumVirtRegs();
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CurrentVRegDefs.setUniverse(NumVirtRegs);
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CurrentVRegUses.setUniverse(NumVirtRegs);
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assert(VRegDefs.empty() && "Only BuildSchedGraph may access VRegDefs");
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VRegUses.clear();
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VRegUses.setUniverse(NumVirtRegs);
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VRegDefs.setUniverse(MRI.getNumVirtRegs());
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VRegUses.setUniverse(MRI.getNumVirtRegs());
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// Model data dependencies between instructions being scheduled and the
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// ExitSU.
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@ -899,7 +808,6 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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RPTracker->recede(/*LiveUses=*/nullptr, PDiff);
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assert(RPTracker->getPos() == std::prev(MII) &&
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"RPTracker can't find MI");
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collectVRegUses(SU);
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}
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assert(
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@ -1149,8 +1057,7 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
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Defs.clear();
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Uses.clear();
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CurrentVRegDefs.clear();
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CurrentVRegUses.clear();
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||||
VRegDefs.clear();
|
||||
PendingLoads.clear();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
|
||||
; FUNC-LABEL: {{^}}width_2d:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[2].Z
|
||||
; EG: MOV [[VAL]], KC0[2].Z
|
||||
define void @width_2d (%opencl.image2d_t addrspace(1)* %in,
|
||||
i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
|
@ -19,7 +19,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}width_3d:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[2].Z
|
||||
; EG: MOV [[VAL]], KC0[2].Z
|
||||
define void @width_3d (%opencl.image3d_t addrspace(1)* %in,
|
||||
i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
|
@ -36,7 +36,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}height_2d:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[2].W
|
||||
; EG: MOV [[VAL]], KC0[2].W
|
||||
define void @height_2d (%opencl.image2d_t addrspace(1)* %in,
|
||||
i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
|
@ -49,7 +49,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}height_3d:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[2].W
|
||||
; EG: MOV [[VAL]], KC0[2].W
|
||||
define void @height_3d (%opencl.image3d_t addrspace(1)* %in,
|
||||
i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
|
@ -66,7 +66,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}depth_3d:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[3].X
|
||||
; EG: MOV [[VAL]], KC0[3].X
|
||||
define void @depth_3d (%opencl.image3d_t addrspace(1)* %in,
|
||||
i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
|
@ -83,7 +83,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}data_type_2d:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[3].Y
|
||||
; EG: MOV [[VAL]], KC0[3].Y
|
||||
define void @data_type_2d (%opencl.image2d_t addrspace(1)* %in,
|
||||
i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
|
@ -96,7 +96,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}data_type_3d:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[3].Y
|
||||
; EG: MOV [[VAL]], KC0[3].Y
|
||||
define void @data_type_3d (%opencl.image3d_t addrspace(1)* %in,
|
||||
i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
|
@ -113,7 +113,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}channel_order_2d:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[3].Z
|
||||
; EG: MOV [[VAL]], KC0[3].Z
|
||||
define void @channel_order_2d (%opencl.image2d_t addrspace(1)* %in,
|
||||
i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
|
@ -126,7 +126,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}channel_order_3d:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[3].Z
|
||||
; EG: MOV [[VAL]], KC0[3].Z
|
||||
define void @channel_order_3d (%opencl.image3d_t addrspace(1)* %in,
|
||||
i32 addrspace(1)* %out) {
|
||||
entry:
|
||||
|
|
@ -145,7 +145,7 @@ entry:
|
|||
;
|
||||
; FUNC-LABEL: {{^}}image_arg_2nd:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[4].Z
|
||||
; EG: MOV [[VAL]], KC0[4].Z
|
||||
define void @image_arg_2nd (%opencl.image3d_t addrspace(1)* %in1,
|
||||
i32 %x,
|
||||
%opencl.image2d_t addrspace(1)* %in2,
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@
|
|||
; ADD_INT literal.x KC0[2].Z, 5
|
||||
|
||||
; CHECK: {{^}}i32_literal:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: ADD_INT * {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.y
|
||||
; CHECK: ADD_INT {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 5
|
||||
define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
|
|
@ -24,8 +24,8 @@ entry:
|
|||
; ADD literal.x KC0[2].Z, 5.0
|
||||
|
||||
; CHECK: {{^}}float_literal:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: ADD * {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.y
|
||||
; CHECK: ADD {{\** *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.0
|
||||
define void @float_literal(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
|
||||
; FUNC-LABEL: {{^}}read_workdim:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[2].Z
|
||||
; EG: MOV [[VAL]], KC0[2].Z
|
||||
|
||||
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb
|
||||
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s
|
||||
|
||||
; R600: {{^}}amdgpu_trunc:
|
||||
; R600: TRUNC {{\*? *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z
|
||||
; R600: TRUNC T{{[0-9]+\.[XYZW]}}, KC0[2].Z
|
||||
; SI: {{^}}amdgpu_trunc:
|
||||
; SI: v_trunc_f32
|
||||
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
|
||||
; FUNC-LABEL: {{^}}local_size_x:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[1].Z
|
||||
; EG: MOV [[VAL]], KC0[1].Z
|
||||
|
||||
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
|
||||
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
|
||||
|
|
@ -23,7 +23,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}local_size_y:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[1].W
|
||||
; EG: MOV [[VAL]], KC0[1].W
|
||||
|
||||
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
|
||||
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
|
||||
|
|
@ -38,7 +38,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}local_size_z:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV * [[VAL]], KC0[2].X
|
||||
; EG: MOV [[VAL]], KC0[2].X
|
||||
|
||||
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
|
||||
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
|
||||
|
|
|
|||
|
|
@ -153,7 +153,7 @@ define void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, i64 %a, i64 %b) {
|
|||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}or_i1:
|
||||
; EG: OR_INT * {{\** *}}T{{[0-9]+\.[XYZW], PS, PV\.[XYZW]}}
|
||||
; EG: OR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
|
||||
|
||||
; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
|
||||
define void @or_i1(i32 addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
; SET*DX10 instructions.
|
||||
|
||||
; CHECK: {{^}}fcmp_une_select_fptosi:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETNE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
|
||||
; CHECK: SETNE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_une_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -19,8 +19,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_une_select_i32:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETNE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
|
||||
; CHECK: SETNE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_une_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -31,8 +31,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_oeq_select_fptosi:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
|
||||
; CHECK: SETE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_oeq_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -45,8 +45,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_oeq_select_i32:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
|
||||
; CHECK: SETE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_oeq_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -57,8 +57,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_ogt_select_fptosi:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
|
||||
; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ogt_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -71,8 +71,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_ogt_select_i32:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
|
||||
; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ogt_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -83,8 +83,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_oge_select_fptosi:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
|
||||
; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_oge_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -97,8 +97,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_oge_select_i32:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.y,
|
||||
; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, literal.x,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_oge_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -109,8 +109,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_ole_select_fptosi:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
|
||||
; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ole_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -123,8 +123,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_ole_select_i32:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGE_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
|
||||
; CHECK: SETGE_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_ole_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -135,8 +135,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_olt_select_fptosi:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
|
||||
; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_olt_select_fptosi(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -149,8 +149,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK: {{^}}fcmp_olt_select_i32:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGT_DX10 * {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.y, KC0[2].Z,
|
||||
; CHECK: SETGT_DX10 {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z,
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @fcmp_olt_select_i32(i32 addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone
|
|||
; SI: buffer_store_dword [[EXTRACT]],
|
||||
|
||||
; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]]
|
||||
; EG: LSHR * [[ADDR]]
|
||||
; EG: BFE_INT * [[RES]], {{.*}}, 0.0, 1
|
||||
; EG: BFE_INT [[RES]], {{.*}}, 0.0, 1
|
||||
; EG-NEXT: LSHR * [[ADDR]]
|
||||
define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) {
|
||||
%shl = shl i32 %in, 31
|
||||
%sext = ashr i32 %shl, 31
|
||||
|
|
|
|||
|
|
@ -53,14 +53,14 @@ define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in
|
|||
ret void
|
||||
}
|
||||
|
||||
;EG-LABEL: {{^}}shl_i64:
|
||||
;EG: {{^}}shl_i64:
|
||||
;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
|
||||
;EG: LSHR {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
|
||||
;EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
|
||||
;EG-DAG: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
|
||||
;EG: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
|
||||
;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
|
||||
;EG-DAG: LSHL {{\*? *}}[[HISMTMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], [[SHIFT]]
|
||||
;EG-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}}
|
||||
;EG-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]|PV.[XYZW]}}
|
||||
;EG-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
|
||||
;EG-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]}}
|
||||
;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
|
||||
;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
|
||||
;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
|
||||
|
|
@ -80,7 +80,7 @@ define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
|
|||
ret void
|
||||
}
|
||||
|
||||
;EG-LABEL: {{^}}shl_v2i64:
|
||||
;EG: {{^}}shl_v2i64:
|
||||
;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
|
||||
;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
|
||||
;EG-DAG: LSHR {{\*? *}}[[COMPSHA]]
|
||||
|
|
|
|||
|
|
@ -70,11 +70,11 @@ entry:
|
|||
;EG-LABEL: {{^}}ashr_i64_2:
|
||||
;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
|
||||
;EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
|
||||
;EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
|
||||
;EG-DAG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
|
||||
;EG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
|
||||
;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
|
||||
;EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
|
||||
;EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}}
|
||||
;EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|PV.[XYZW]|[[SHIFT]]}}
|
||||
;EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
|
||||
;EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
|
||||
;EG-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
|
||||
;EG-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
|
||||
;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
|
||||
|
|
|
|||
|
|
@ -65,14 +65,14 @@ define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %i
|
|||
|
||||
; EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
|
||||
; EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
|
||||
; EG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
|
||||
; EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
|
||||
; EG-DAG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
|
||||
; EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
|
||||
; EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}}
|
||||
; EG-DAG: LSHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]|PV\.[XYZW]}}
|
||||
; EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
|
||||
; EG-DAG: LSHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
|
||||
; EG-DAG: LSHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|[[SHIFT]]}}
|
||||
; EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
|
||||
; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]|PS}}
|
||||
; EG-DAG: LSHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], [[SHIFT]]
|
||||
; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
|
||||
; EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
|
||||
define void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
|
||||
%b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
; These tests are for condition codes that are not supported by the hardware
|
||||
|
||||
; CHECK-LABEL: {{^}}slt:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z
|
||||
; CHECK: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 5(7.006492e-45)
|
||||
define void @slt(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
|
|
@ -15,8 +15,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}ult_i32:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z
|
||||
; CHECK: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 5(7.006492e-45)
|
||||
define void @ult_i32(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
|
|
@ -40,8 +40,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}ult_float_native:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGE {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}}
|
||||
; CHECK: SETGE T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
|
||||
; CHECK-NEXT: LSHR *
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @ult_float_native(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -52,8 +52,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}olt:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z
|
||||
; CHECK: SETGT T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR *
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @olt(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -64,8 +64,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}sle:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z
|
||||
; CHECK: SETGT_INT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 6(8.407791e-45)
|
||||
define void @sle(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
|
|
@ -76,8 +76,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}ule_i32:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z
|
||||
; CHECK: SETGT_UINT {{\** *}}T{{[0-9]+\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR
|
||||
; CHECK-NEXT: 6(8.407791e-45)
|
||||
define void @ule_i32(i32 addrspace(1)* %out, i32 %in) {
|
||||
entry:
|
||||
|
|
@ -101,8 +101,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}ule_float_native:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGT {{\*? *}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, {{literal\.[xy]}}
|
||||
; CHECK: SETGT T{{[0-9]\.[XYZW]}}, KC0[2].Z, literal.x
|
||||
; CHECK-NEXT: LSHR *
|
||||
; CHECK-NEXT: 1084227584(5.000000e+00)
|
||||
define void @ule_float_native(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
@ -113,8 +113,8 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}ole:
|
||||
; CHECK: LSHR
|
||||
; CHECK-NEXT: SETGE {{\*? *}}T{{[0-9]\.[XYZW]}}, {{literal\.[xy]}}, KC0[2].Z
|
||||
; CHECK: SETGE T{{[0-9]\.[XYZW]}}, literal.x, KC0[2].Z
|
||||
; CHECK-NEXT: LSHR *
|
||||
; CHECK-NEXT:1084227584(5.000000e+00)
|
||||
define void @ole(float addrspace(1)* %out, float %in) {
|
||||
entry:
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
|
||||
; FUNC-LABEL: {{^}}ngroups_x:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV {{\*? *}}[[VAL]], KC0[0].X
|
||||
; EG: MOV [[VAL]], KC0[0].X
|
||||
|
||||
; HSA: .amd_kernel_code_t
|
||||
|
||||
|
|
@ -38,7 +38,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}ngroups_y:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y
|
||||
; EG: MOV [[VAL]], KC0[0].Y
|
||||
|
||||
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1
|
||||
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
|
||||
|
|
@ -53,7 +53,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}ngroups_z:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z
|
||||
; EG: MOV [[VAL]], KC0[0].Z
|
||||
|
||||
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2
|
||||
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
|
||||
|
|
@ -68,7 +68,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}global_size_x:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV {{\*? *}}[[VAL]], KC0[0].W
|
||||
; EG: MOV [[VAL]], KC0[0].W
|
||||
|
||||
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3
|
||||
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc
|
||||
|
|
@ -83,7 +83,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}global_size_y:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV {{\*? *}}[[VAL]], KC0[1].X
|
||||
; EG: MOV [[VAL]], KC0[1].X
|
||||
|
||||
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
|
||||
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10
|
||||
|
|
@ -98,7 +98,7 @@ entry:
|
|||
|
||||
; FUNC-LABEL: {{^}}global_size_z:
|
||||
; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
|
||||
; EG: MOV {{\*? *}}[[VAL]], KC0[1].Y
|
||||
; EG: MOV [[VAL]], KC0[1].Y
|
||||
|
||||
; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5
|
||||
; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in
|
|||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}xor_i1:
|
||||
; EG: XOR_INT {{\** *}}{{T[0-9]+\.[XYZW]}}, {{PS|PV\.[XYZW]}}, {{PS|PV\.[XYZW]}}
|
||||
; EG: XOR_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], PS}}
|
||||
|
||||
; SI-DAG: v_cmp_le_f32_e32 [[CMP0:vcc]], 0, {{v[0-9]+}}
|
||||
; SI-DAG: v_cmp_le_f32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 1.0, {{v[0-9]+}}
|
||||
|
|
|
|||
Loading…
Reference in New Issue