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RegScavenger: Use Register 

llvm-svn: 369794
This commit is contained in:
Matt Arsenault 2019-08-23 18:25:34 +00:00
parent 1fd2e69e28
commit 2fd1afe8ef
2 changed files with 29 additions and 29 deletions
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24
llvm/include/llvm/CodeGen/RegisterScavenging.h
View File

@ -51,7 +51,7 @@ class RegScavenger {
/// If non-zero, the specific register is currently being
/// scavenged. That is, it is spilled to this scavenging stack slot.
unsigned Reg = 0;
Register Reg;
/// The instruction that restores the scavenged register from stack.
const MachineInstr *Restore = nullptr;
@ -119,14 +119,14 @@ public:
MachineBasicBlock::iterator getCurrentPosition() const { return MBBI; }
/// Return if a specific register is currently used.
bool isRegUsed(unsigned Reg, bool includeReserved = true) const;
bool isRegUsed(Register Reg, bool includeReserved = true) const;
/// Return all available registers in the register class in Mask.
BitVector getRegsAvailable(const TargetRegisterClass *RC);
/// Find an unused register of the specified register class.
/// Return 0 if none is found.
unsigned FindUnusedReg(const TargetRegisterClass *RC) const;
Register FindUnusedReg(const TargetRegisterClass *RC) const;
/// Add a scavenging frame index.
void addScavengingFrameIndex(int FI) {
@ -160,10 +160,10 @@ public:
///
/// If \p AllowSpill is false, fail if a spill is required to make the
/// register available, and return NoRegister.
unsigned scavengeRegister(const TargetRegisterClass *RC,
Register scavengeRegister(const TargetRegisterClass *RC,
MachineBasicBlock::iterator I, int SPAdj,
bool AllowSpill = true);
unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
bool AllowSpill = true) {
return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
}
@ -177,17 +177,17 @@ public:
///
/// If \p AllowSpill is false, fail if a spill is required to make the
/// register available, and return NoRegister.
unsigned scavengeRegisterBackwards(const TargetRegisterClass &RC,
Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
MachineBasicBlock::iterator To,
bool RestoreAfter, int SPAdj,
bool AllowSpill = true);
/// Tell the scavenger a register is used.
void setRegUsed(unsigned Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
void setRegUsed(Register Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
private:
/// Returns true if a register is reserved. It is never "unused".
bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
bool isReserved(Register Reg) const { return MRI->isReserved(Reg); }
/// setUsed / setUnused - Mark the state of one or a number of register units.
///
@ -203,16 +203,16 @@ private:
void determineKillsAndDefs();
/// Add all Reg Units that Reg contains to BV.
void addRegUnits(BitVector &BV, unsigned Reg);
void addRegUnits(BitVector &BV, Register Reg);
/// Remove all Reg Units that \p Reg contains from \p BV.
void removeRegUnits(BitVector &BV, unsigned Reg);
void removeRegUnits(BitVector &BV, Register Reg);
/// Return the candidate register that is unused for the longest after
/// StartMI. UseMI is set to the instruction where the search stopped.
///
/// No more than InstrLimit instructions are inspected.
unsigned findSurvivorReg(MachineBasicBlock::iterator StartMI,
Register findSurvivorReg(MachineBasicBlock::iterator StartMI,
BitVector &Candidates,
unsigned InstrLimit,
MachineBasicBlock::iterator &UseMI);
@ -225,7 +225,7 @@ private:
/// Spill a register after position \p After and reload it before position
/// \p UseMI.
ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
MachineBasicBlock::iterator Before,
MachineBasicBlock::iterator &UseMI);
};

34
llvm/lib/CodeGen/RegisterScavenging.cpp
View File

@ -49,7 +49,7 @@ using namespace llvm;
STATISTIC(NumScavengedRegs, "Number of frame index regs scavenged");
void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) {
void RegScavenger::setRegUsed(Register Reg, LaneBitmask LaneMask) {
LiveUnits.addRegMasked(Reg, LaneMask);
}
@ -96,12 +96,12 @@ void RegScavenger::enterBasicBlockEnd(MachineBasicBlock &MBB) {
}
}
void RegScavenger::addRegUnits(BitVector &BV, unsigned Reg) {
void RegScavenger::addRegUnits(BitVector &BV, Register Reg) {
for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
BV.set(*RUI);
}
void RegScavenger::removeRegUnits(BitVector &BV, unsigned Reg) {
void RegScavenger::removeRegUnits(BitVector &BV, Register Reg) {
for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
BV.reset(*RUI);
}
@ -278,14 +278,14 @@ void RegScavenger::backward() {
--MBBI;
}
bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const {
bool RegScavenger::isRegUsed(Register Reg, bool includeReserved) const {
if (isReserved(Reg))
return includeReserved;
return !LiveUnits.available(Reg);
}
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
for (unsigned Reg : *RC) {
Register RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
for (Register Reg : *RC) {
if (!isRegUsed(Reg)) {
LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI)
<< "\n");
@ -297,13 +297,13 @@ unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
BitVector Mask(TRI->getNumRegs());
for (unsigned Reg : *RC)
for (Register Reg : *RC)
if (!isRegUsed(Reg))
Mask.set(Reg);
return Mask;
}
unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
Register RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
BitVector &Candidates,
unsigned InstrLimit,
MachineBasicBlock::iterator &UseMI) {
@ -457,7 +457,7 @@ static unsigned getFrameIndexOperandNum(MachineInstr &MI) {
}
RegScavenger::ScavengedInfo &
RegScavenger::spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
MachineBasicBlock::iterator Before,
MachineBasicBlock::iterator &UseMI) {
// Find an available scavenging slot with size and alignment matching
@ -531,7 +531,7 @@ RegScavenger::spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
return Scavenged[SI];
}
unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
Register RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
MachineBasicBlock::iterator I,
int SPAdj, bool AllowSpill) {
MachineInstr &MI = *I;
@ -556,7 +556,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
// Find the register whose use is furthest away.
MachineBasicBlock::iterator UseMI;
unsigned SReg = findSurvivorReg(I, Candidates, 25, UseMI);
Register SReg = findSurvivorReg(I, Candidates, 25, UseMI);
// If we found an unused register there is no reason to spill it.
if (!isRegUsed(SReg)) {
@ -576,7 +576,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
return SReg;
}
unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
Register RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
MachineBasicBlock::iterator To,
bool RestoreAfter, int SPAdj,
bool AllowSpill) {
@ -620,8 +620,8 @@ unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
/// \p ReserveAfter controls whether the scavenged register needs to be reserved
/// after the current instruction, otherwise it will only be reserved before the
/// current instruction.
static unsigned scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS,
unsigned VReg, bool ReserveAfter) {
static Register scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS,
Register VReg, bool ReserveAfter) {
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
#ifndef NDEBUG
// Verify that all definitions and uses are in the same basic block.
@ -664,7 +664,7 @@ static unsigned scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS,
// spill/reload if necessary.
int SPAdj = 0;
const TargetRegisterClass &RC = *MRI.getRegClass(VReg);
unsigned SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
Register SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
ReserveAfter, SPAdj);
MRI.replaceRegWith(VReg, SReg);
++NumScavengedRegs;
@ -704,7 +704,7 @@ static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI,
if (!MO.readsReg())
continue;
unsigned SReg = scavengeVReg(MRI, RS, Reg, true);
Register SReg = scavengeVReg(MRI, RS, Reg, true);
N->addRegisterKilled(SReg, &TRI, false);
RS.setRegUsed(SReg);
}
@ -730,7 +730,7 @@ static bool scavengeFrameVirtualRegsInBlock(MachineRegisterInfo &MRI,
NextInstructionReadsVReg = true;
}
if (MO.isDef()) {
unsigned SReg = scavengeVReg(MRI, RS, Reg, false);
Register SReg = scavengeVReg(MRI, RS, Reg, false);
I->addRegisterDead(SReg, &TRI, false);
}
}