From 2fc939c809a0b54ca62ff7832253968f54833dd6 Mon Sep 17 00:00:00 2001
From: Eli Friedman <eli.friedman@gmail.com>
Date: Fri, 19 Jun 2009 07:00:55 +0000
Subject: [PATCH] Fix for PR2484: add an SSE1 pattern for a shuffle we normally
 prefer to handle with an SSE2 instruction.

llvm-svn: 73760
---
 llvm/lib/Target/X86/X86InstrSSE.td                       | 6 ++++++
 .../CodeGen/X86/2009-06-18-movlp-shuffle-register.ll     | 9 +++++++++
 2 files changed, 15 insertions(+)
 create mode 100644 llvm/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll

diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td
index b44c7a693ef7..5d6ef36414a5 100644
--- a/llvm/lib/Target/X86/X86InstrSSE.td
+++ b/llvm/lib/Target/X86/X86InstrSSE.td
@@ -3027,6 +3027,12 @@ def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
           (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
 }
 
+// vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
+// fall back to this for SSE1)
+def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
+          (SHUFPSrri VR128:$src2, VR128:$src1, 
+                     (SHUFFLE_get_shuf_imm VR128:$src3))>, Requires<[HasSSE1]>;
+
 // Set lowest element and zero upper elements.
 let AddedComplexity = 15 in
 def : Pat<(v2f64 (movl immAllZerosV_bc, VR128:$src)),
diff --git a/llvm/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll b/llvm/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll
new file mode 100644
index 000000000000..d6ff5b6803e3
--- /dev/null
+++ b/llvm/test/CodeGen/X86/2009-06-18-movlp-shuffle-register.ll
@@ -0,0 +1,9 @@
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse,-sse2
+; PR2484
+
+define <4 x float> @f4523(<4 x float> %a,<4 x float> %b) nounwind {
+entry:
+%shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4,i32
+5,i32 2,i32 3>
+ret <4 x float> %shuffle
+}