forked from OSchip/llvm-project
[AArch64] Generate FP16 vector compare instructions.
https://reviews.llvm.org/D58561 llvm-svn: 355050
This commit is contained in:
Abderrazek Zaafrani
parent
aa03bcd23c
commit
2fc498a652
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@ -7779,8 +7779,8 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
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// Make v4f16 (only) fcmp operations utilise vector instructions
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// v8f16 support will be a litle more complicated
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if (LHS.getValueType().getVectorElementType() == MVT::f16) {
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if (!FullFP16 && LHS.getValueType().getVectorNumElements() == 4) {
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if (!FullFP16 && LHS.getValueType().getVectorElementType() == MVT::f16) {
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if (LHS.getValueType().getVectorNumElements() == 4) {
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LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS);
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RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS);
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SDValue NewSetcc = DAG.getSetCC(dl, MVT::v4i16, LHS, RHS, CC);
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@ -7790,8 +7790,8 @@ SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
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return SDValue();
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}
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assert(LHS.getValueType().getVectorElementType() == MVT::f32 ||
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LHS.getValueType().getVectorElementType() == MVT::f64);
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assert((!FullFP16 && LHS.getValueType().getVectorElementType() != MVT::f16) ||
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LHS.getValueType().getVectorElementType() != MVT::f128);
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// Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
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// clean. Some of them require two branches to implement.
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@ -304,15 +304,7 @@ define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_une:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ne
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ne
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ne
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ne
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; CHECK-FP16: ret
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; CHECK-FP16: fcmeq v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp une <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -330,15 +322,8 @@ define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_ueq:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, eq
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, eq
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, eq
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, eq
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; CHECK-FP16: ret
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; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
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; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp ueq <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -354,15 +339,7 @@ define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_ugt:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, hi
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, hi
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, hi
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, hi
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; CHECK-FP16: ret
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; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp ugt <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -378,15 +355,7 @@ define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_uge:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, pl
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, pl
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, pl
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, pl
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; CHECK-FP16: ret
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; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp uge <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -402,15 +371,7 @@ define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_ult:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, lt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, lt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, lt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, lt
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; CHECK-FP16: ret
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; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp ult <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -426,15 +387,7 @@ define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_ule:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, le
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, le
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, le
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, le
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; CHECK-FP16: ret
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; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp ule <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -452,15 +405,8 @@ define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_uno:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, vs
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, vs
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, vs
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, vs
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; CHECK-FP16: ret
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; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
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; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp uno <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -477,15 +423,8 @@ define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_one:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, mi
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, mi
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, mi
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, mi
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; CHECK-FP16: ret
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; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
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; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp one <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -500,15 +439,7 @@ define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_oeq:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, eq
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, eq
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, eq
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, eq
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; CHECK-FP16: ret
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; CHECK-FP16: fcmeq v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp oeq <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -523,15 +454,7 @@ define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_ogt:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, gt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, gt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, gt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, gt
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; CHECK-FP16: ret
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; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp ogt <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -546,15 +469,7 @@ define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_oge:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ge
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ge
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ge
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ge
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; CHECK-FP16: ret
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; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp oge <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -569,15 +484,7 @@ define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_olt:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, mi
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, mi
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, mi
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, mi
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; CHECK-FP16: ret
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; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp olt <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -592,15 +499,7 @@ define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_ole:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ls
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ls
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ls
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, ls
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; CHECK-FP16: ret
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; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp ole <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -617,15 +516,8 @@ define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_ord:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, vc
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, vc
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, vc
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; CHECK-FP16: fcmp h{{.}}, h{{.}}
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; CHECK-FP16: csetm {{.*}}, vc
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; CHECK-FP16: ret
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; CHECK-FP16: fcmge v{{[0-9]}}.4h, v{{[0-9]}}.4h
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; CHECK-FP16: fcmgt v{{[0-9]}}.4h, v{{[0-9]}}.4h
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%1 = fcmp ord <4 x half> %a, %b
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ret <4 x i1> %1
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}
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@ -450,14 +450,7 @@ define <8 x i1> @test_fcmp_une(<8 x half> %a, <8 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_une:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h
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%1 = fcmp une <8 x half> %a, %b
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ret <8 x i1> %1
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@ -468,14 +461,8 @@ define <8 x i1> @test_fcmp_ueq(<8 x half> %a, <8 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_ueq:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
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; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
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%1 = fcmp ueq <8 x half> %a, %b
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ret <8 x i1> %1
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@ -486,14 +473,7 @@ define <8 x i1> @test_fcmp_ugt(<8 x half> %a, <8 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_ugt:
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; CHECK-FP16-NOT: fcvt
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
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; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
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%1 = fcmp ugt <8 x half> %a, %b
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ret <8 x i1> %1
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@ -504,14 +484,7 @@ define <8 x i1> @test_fcmp_uge(<8 x half> %a, <8 x half> %b) #0 {
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; CHECK-FP16-LABEL: test_fcmp_uge:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp uge <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
@ -522,14 +495,7 @@ define <8 x i1> @test_fcmp_ult(<8 x half> %a, <8 x half> %b) #0 {
|
|||
|
||||
; CHECK-FP16-LABEL: test_fcmp_ult:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp ult <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
@ -540,14 +506,7 @@ define <8 x i1> @test_fcmp_ule(<8 x half> %a, <8 x half> %b) #0 {
|
|||
|
||||
; CHECK-FP16-LABEL: test_fcmp_ule:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp ule <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
@ -558,14 +517,8 @@ define <8 x i1> @test_fcmp_uno(<8 x half> %a, <8 x half> %b) #0 {
|
|||
|
||||
; CHECK-FP16-LABEL: test_fcmp_uno:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp uno <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
@ -576,14 +529,8 @@ define <8 x i1> @test_fcmp_one(<8 x half> %a, <8 x half> %b) #0 {
|
|||
|
||||
; CHECK-FP16-LABEL: test_fcmp_one:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp one <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
@ -594,14 +541,7 @@ define <8 x i1> @test_fcmp_oeq(<8 x half> %a, <8 x half> %b) #0 {
|
|||
|
||||
; CHECK-FP16-LABEL: test_fcmp_oeq:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmeq v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp oeq <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
@ -612,14 +552,7 @@ define <8 x i1> @test_fcmp_ogt(<8 x half> %a, <8 x half> %b) #0 {
|
|||
|
||||
; CHECK-FP16-LABEL: test_fcmp_ogt:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp ogt <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
@ -630,14 +563,7 @@ define <8 x i1> @test_fcmp_oge(<8 x half> %a, <8 x half> %b) #0 {
|
|||
|
||||
; CHECK-FP16-LABEL: test_fcmp_oge:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp oge <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
@ -648,14 +574,7 @@ define <8 x i1> @test_fcmp_olt(<8 x half> %a, <8 x half> %b) #0 {
|
|||
|
||||
; CHECK-FP16-LABEL: test_fcmp_olt:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp olt <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
@ -666,14 +585,7 @@ define <8 x i1> @test_fcmp_ole(<8 x half> %a, <8 x half> %b) #0 {
|
|||
|
||||
; CHECK-FP16-LABEL: test_fcmp_ole:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp ole <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
@ -684,14 +596,8 @@ define <8 x i1> @test_fcmp_ord(<8 x half> %a, <8 x half> %b) #0 {
|
|||
|
||||
; CHECK-FP16-LABEL: test_fcmp_ord:
|
||||
; CHECK-FP16-NOT: fcvt
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmp h{{[0-9]}}, h{{[0-9]}}
|
||||
; CHECK-FP16-DAG: fcmge v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
; CHECK-FP16-DAG: fcmgt v{{[0-9]}}.8h, v{{[0-9]}}.8h
|
||||
|
||||
%1 = fcmp ord <8 x half> %a, %b
|
||||
ret <8 x i1> %1
|
||||
|
|
|
|||
Loading…
Reference in New Issue