forked from OSchip/llvm-project
[BOLT] Update skipRelocation for aarch64
The ld might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP, add the new case to the skipRelocation for aarch64. Vladislav Khmelevsky, Advanced Software Technology Lab, Huawei Differential Revision: https://reviews.llvm.org/D123334
This commit is contained in:
Vladislav Khmelevsky
parent
b8bac957d1
commit
2f98c5febc
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@ -168,16 +168,17 @@ bool skipRelocationProcessX86(uint64_t Type, uint64_t Contents) {
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bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
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auto IsMov = [](uint64_t Contents) -> bool {
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// The bits 28-23 are 0b100101
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if ((Contents & 0x1f800000) == 0x12800000)
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return true;
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return false;
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return (Contents & 0x1f800000) == 0x12800000;
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};
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auto IsB = [](uint64_t Contents) -> bool {
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// The bits 31-26 are 0b000101
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if ((Contents & 0xfc000000) == 0x14000000)
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return true;
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return false;
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return (Contents & 0xfc000000) == 0x14000000;
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};
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auto IsAdr = [](uint64_t Contents) -> bool {
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// The bits 31-24 are 0b0xx10000
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return (Contents & 0x9f000000) == 0x10000000;
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};
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auto IsNop = [](uint64_t Contents) -> bool { return Contents == 0xd503201f; };
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@ -205,7 +206,7 @@ bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
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}
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}
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// The ld might replace load/store instruction with jump and
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// The linker might replace load/store instruction with jump and
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// veneer due to errata 843419
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// https://documentation-service.arm.com/static/5fa29fddb209f547eebd361d
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// Thus load/store relocations for these instructions must be ignored
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@ -223,6 +224,18 @@ bool skipRelocationProcessAArch64(uint64_t Type, uint64_t Contents) {
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}
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}
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// The linker might relax ADRP+ADD or ADRP+LDR sequences to the ADR+NOP
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switch (Type) {
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default:
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break;
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case ELF::R_AARCH64_ADR_PREL_PG_HI21:
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case ELF::R_AARCH64_ADD_ABS_LO12_NC:
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case ELF::R_AARCH64_ADR_GOT_PAGE:
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case ELF::R_AARCH64_LD64_GOT_LO12_NC:
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if (IsAdr(Contents))
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return true;
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}
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return false;
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}
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@ -0,0 +1,172 @@
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--- !ELF
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FileHeader:
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Class: ELFCLASS64
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Data: ELFDATA2LSB
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Type: ET_DYN
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Machine: EM_AARCH64
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Entry: 0x10364
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ProgramHeaders:
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- Type: PT_PHDR
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Flags: [ PF_R ]
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VAddr: 0x40
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Align: 0x8
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- Type: PT_INTERP
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Flags: [ PF_R ]
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FirstSec: .interp
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LastSec: .interp
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VAddr: 0x238
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- Type: PT_LOAD
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Flags: [ PF_R ]
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FirstSec: .interp
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LastSec: .dynamic
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Align: 0x10000
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- Type: PT_LOAD
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Flags: [ PF_X, PF_R ]
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FirstSec: .text
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LastSec: .text
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VAddr: 0x10348
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Align: 0x10000
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- Type: PT_LOAD
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Flags: [ PF_W, PF_R ]
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FirstSec: .dynamic
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LastSec: .got
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VAddr: 0x20388
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Align: 0x10000
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- Type: PT_DYNAMIC
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Flags: [ PF_W, PF_R ]
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FirstSec: .dynamic
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LastSec: .dynamic
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VAddr: 0x20388
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Align: 0x8
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- Type: PT_GNU_RELRO
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Flags: [ PF_R ]
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FirstSec: .dynamic
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LastSec: .got
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VAddr: 0x20388
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- Type: PT_GNU_STACK
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Flags: [ PF_W, PF_R ]
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Align: 0x0
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Sections:
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- Name: .interp
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Type: SHT_PROGBITS
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Flags: [ SHF_ALLOC ]
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Address: 0x238
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AddressAlign: 0x1
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Content: 2F6C69622F6C642D6C696E75782D616172636836342E736F2E3100
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- Name: .dynsym
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Type: SHT_DYNSYM
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Flags: [ SHF_ALLOC ]
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Address: 0x258
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Link: .dynstr
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AddressAlign: 0x8
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- Name: .dynstr
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Type: SHT_STRTAB
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Flags: [ SHF_ALLOC ]
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Address: 0x28C
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AddressAlign: 0x1
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- Name: .rela.dyn
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Type: SHT_RELA
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Flags: [ SHF_ALLOC ]
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Address: 0x290
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Link: .dynsym
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AddressAlign: 0x8
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Relocations:
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- Offset: 0x20448
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Type: R_AARCH64_RELATIVE
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Addend: 66432
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- Name: .text
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Type: SHT_PROGBITS
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Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
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Address: 0x10348
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AddressAlign: 0x4
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Content: FF4300D1E00700F9E80740F908014092E003082AFF430091C0035FD6FD7BBFA9FD0300911F2003D580000010F5FFFF97FD7BC1A8C0035FD6C0035FD6
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- Name: .dynamic
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Type: SHT_DYNAMIC
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Flags: [ SHF_WRITE, SHF_ALLOC ]
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Address: 0x20388
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Link: .dynstr
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AddressAlign: 0x8
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Entries:
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- Tag: DT_FLAGS_1
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Value: 0x8000000
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- Tag: DT_RELA
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Value: 0x290
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- Tag: DT_RELASZ
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Value: 0x18
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- Tag: DT_RELAENT
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Value: 0x18
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- Tag: DT_RELACOUNT
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Value: 0x1
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- Tag: DT_SYMTAB
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Value: 0x258
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Value: 0x18
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Value: 0x28C
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Value: 0x1
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- Tag: DT_GNU_HASH
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Value: 0x270
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- Tag: DT_NULL
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Value: 0x0
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- Name: .got
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Type: SHT_PROGBITS
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Flags: [ SHF_WRITE, SHF_ALLOC ]
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Address: 0x20448
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AddressAlign: 0x8
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Content: '0000000000000000'
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- Name: .rela.text
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Type: SHT_RELA
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Flags: [ SHF_INFO_LINK ]
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Link: .symtab
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AddressAlign: 0x8
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Info: .text
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Relocations:
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- Offset: 0x1036C
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Symbol: foo2
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Type: R_AARCH64_ADR_GOT_PAGE
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- Offset: 0x10370
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Symbol: foo2
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Type: R_AARCH64_LD64_GOT_LO12_NC
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- Offset: 0x10374
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Symbol: foo
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Type: R_AARCH64_CALL26
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Symbols:
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- Name: .text
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Type: STT_SECTION
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Section: .text
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Value: 0x10348
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- Name: ex2.c
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Type: STT_FILE
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Index: SHN_ABS
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- Name: '$x.0 (1)'
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Section: .text
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Value: 0x10380
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- Name: .interp
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Type: STT_SECTION
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Section: .interp
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Value: 0x238
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- Name: _DYNAMIC
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Section: .dynamic
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Value: 0x20388
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Other: [ STV_HIDDEN ]
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- Name: foo
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Type: STT_FUNC
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Section: .text
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Binding: STB_GLOBAL
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Value: 0x10348
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Size: 0x1C
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- Name: _start
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Type: STT_FUNC
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Section: .text
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Binding: STB_GLOBAL
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Value: 0x10364
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Size: 0x1C
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- Name: foo2
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Type: STT_FUNC
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Section: .text
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Binding: STB_GLOBAL
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Value: 0x10380
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Size: 0x4
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DynamicSymbols: []
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...
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@ -0,0 +1,8 @@
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// This test checks that the binary with relaxed ADRP+LDR instructions is
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// processed normally with BOLT and the ADR instruction address is recognized
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// normally.
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RUN: yaml2obj %p/Inputs/skip-got-rel.yaml &> %t.exe
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RUN: llvm-bolt %t.exe -o /dev/null -print-cfg -print-only=_start | FileCheck %s
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CHECK: adr x0, foo2
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@ -1,9 +1,16 @@
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// This test checks that the pointers to PLT are properly updated.
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// The test is using lld linker.
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// RUN: %clang %cflags -no-pie %p/../Inputs/plt.c -fuse-ld=lld \
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// RUN: -o %t.lld.exe -Wl,-q
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// RUN: llvm-bolt %t.lld.exe -o %t.lld.bolt.exe -use-old-text=0 -lite=0
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// RUN: %t.lld.bolt.exe | FileCheck %s
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// Non-PIE:
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RUN: %clang %cflags -no-pie %p/../Inputs/plt.c -fuse-ld=lld \
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RUN: -o %t.lld.exe -Wl,-q
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RUN: llvm-bolt %t.lld.exe -o %t.lld.bolt.exe -use-old-text=0 -lite=0
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RUN: %t.lld.bolt.exe | FileCheck %s
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// CHECK: Test completed
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// PIE:
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RUN: %clang %cflags -fPIC -pie %p/../Inputs/plt.c -fuse-ld=lld \
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RUN: -o %t.lld.pie.exe -Wl,-q
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RUN: llvm-bolt %t.lld.pie.exe -o %t.lld.bolt.pie.exe -use-old-text=0 -lite=0
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RUN: %t.lld.bolt.pie.exe | FileCheck %s
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CHECK: Test completed
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