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Add FSQRT, FSIN, FCOS nodes, patch contributed by Morten Ofstad 

llvm-svn: 21605
This commit is contained in:
Chris Lattner 2005-04-28 21:44:03 +00:00
parent 16983ca865
commit 2f82d2d58a
2 changed files with 7 additions and 4 deletions
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6
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
View File

@ -168,9 +168,9 @@ namespace ISD {
// FP_EXTEND - Extend a smaller FP type into a larger FP type.
FP_EXTEND,
// FNEG, FABS - Perform unary floating point negation and absolute value
// operations.
FNEG, FABS,
// FNEG, FABS, FSQRT, FSIN, FCOS - Perform unary floating point negation,
// absolute value, square root, sine and cosine operations.
FNEG, FABS, FSQRT, FSIN, FCOS,
// Other operators. LOAD and STORE have token chains as their first
// operand, then the same operands as an LLVM load/store instruction.

5
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1568,6 +1568,9 @@ const char *SDNode::getOperationName() const {
// Unary operators
case ISD::FABS: return "fabs";
case ISD::FNEG: return "fneg";
case ISD::FSQRT: return "fsqrt";
case ISD::FSIN: return "fsin";
case ISD::FCOS: return "fcos";
// Binary operators
case ISD::ADD: return "add";
@ -1593,7 +1596,7 @@ const char *SDNode::getOperationName() const {
case ISD::SRA_PARTS: return "sra_parts";
case ISD::SRL_PARTS: return "srl_parts";
// Conversion operators.
// Conversion operators.
case ISD::SIGN_EXTEND: return "sign_extend";
case ISD::ZERO_EXTEND: return "zero_extend";
case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";