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MachineInstr: introduce explicit_operands and implicit_operands ranges 

Makes iteration over implicit and explicit machine operands more
explicit (har har). Insipired by code review discussion for r205565.

llvm-svn: 205680
This commit is contained in:
David Blaikie 2014-04-05 22:42:04 +00:00
parent 1c42eaeb13
commit 2f7711242a
3 changed files with 18 additions and 7 deletions
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16
llvm/include/llvm/CodeGen/MachineInstr.h
View File

@ -293,6 +293,22 @@ public:
iterator_range<const_mop_iterator> operands() const {
return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
}
iterator_range<mop_iterator> explicit_operands() {
return iterator_range<mop_iterator>(
operands_begin(), operands_begin() + getNumExplicitOperands());
}
iterator_range<const_mop_iterator> explicit_operands() const {
return iterator_range<const_mop_iterator>(
operands_begin(), operands_begin() + getNumExplicitOperands());
}
iterator_range<mop_iterator> implicit_operands() {
return iterator_range<mop_iterator>(explicit_operands().end(),
operands_end());
}
iterator_range<const_mop_iterator> implicit_operands() const {
return iterator_range<const_mop_iterator>(explicit_operands().end(),
operands_end());
}
/// Access to memory operands of the instruction
mmo_iterator memoperands_begin() const { return MemRefs; }

5
llvm/lib/Target/ARM64/ARM64DeadRegisterDefinitionsPass.cpp
View File

@ -50,13 +50,10 @@ char ARM64DeadRegisterDefinitions::ID = 0;
bool ARM64DeadRegisterDefinitions::implicitlyDefinesSubReg(
unsigned Reg,
const MachineInstr *MI) {
for (unsigned i = MI->getNumExplicitOperands(), e = MI->getNumOperands();
i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (const MachineOperand &MO : MI->implicit_operands())
if (MO.isReg() && MO.isDef())
if (TRI->isSubRegister(Reg, MO.getReg()))
return true;
}
return false;
}

4
llvm/lib/Target/R600/AMDGPUMCInstLower.cpp
View File

@ -38,9 +38,7 @@ AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx):
void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (const MachineOperand &MO : MI->explicit_operands()) {
MCOperand MCOp;
switch (MO.getType()) {
default: