maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[PhaseOrdering] Add test case for PR45682 

Ensures that the correct sequence of simplifycfg/instcombine/sroa reduce the IR to just a icmp+assume (which will be dropped in backend)
This commit is contained in:
Simon Pilgrim 2021-04-21 15:06:35 +01:00
parent 68b9b769b5
commit 2f69975683
1 changed files with 37 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
llvm/test/Transforms/PhaseOrdering/pr45682.ll Normal file
View File

@ -0,0 +1,37 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -O3 -S < %s | FileCheck %s
; RUN: opt -passes='default<O3>' -S < %s | FileCheck %s
define void @PR45682(i32 %x, i32 %y) {
; CHECK-LABEL: @PR45682(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[Y:%.*]], 0
; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: ret void
;
entry:
%x.addr = alloca i32, align 4
%y.addr = alloca i32, align 4
store i32 %x, i32* %x.addr, align 4
store i32 %y, i32* %y.addr, align 4
%0 = load i32, i32* %y.addr, align 4
%cmp = icmp sgt i32 %0, 0
call void @llvm.assume(i1 %cmp)
%1 = load i32, i32* %y.addr, align 4
%2 = load i32, i32* %x.addr, align 4
%add = add nsw i32 %2, %1
store i32 %add, i32* %x.addr, align 4
%3 = load i32, i32* %x.addr, align 4
%cmp1 = icmp eq i32 %3, -2147483648
br i1 %cmp1, label %if.then, label %if.end
if.then:
call void @v()
br label %if.end
if.end:
ret void
}
declare void @v()
declare void @llvm.assume(i1)