forked from OSchip/llvm-project
[AMDGPU] Assembler: Basic support for MIMG
Add parsing and printing of image operands. Matches legacy sp3 assembler. Change image instruction order to have data/image/sampler operands in the beginning. This is needed because optional operands in MC are always last. Update SITargetLowering for new order. Add basic MC test. Update CodeGen tests. Review: http://reviews.llvm.org/D17574 llvm-svn: 261995
This commit is contained in:
Nikolay Haustov
parent
f3d6612c0a
commit
2f684f1347
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@ -67,7 +67,12 @@ public:
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ImmTySLC,
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ImmTyTFE,
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ImmTyClamp,
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ImmTyOMod
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ImmTyOMod,
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ImmTyDMask,
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ImmTyUNorm,
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ImmTyDA,
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ImmTyR128,
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ImmTyLWE,
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};
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struct TokOp {
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@ -194,14 +199,31 @@ public:
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return Kind == Register || isInlinableImm();
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}
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bool isImmTy(ImmTy ImmT) const {
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return isImm() && Imm.Type == ImmT;
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}
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bool isClamp() const {
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return isImm() && Imm.Type == ImmTyClamp;
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return isImmTy(ImmTyClamp);
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}
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bool isOMod() const {
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return isImm() && Imm.Type == ImmTyOMod;
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return isImmTy(ImmTyOMod);
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}
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bool isImmModifier() const {
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return Kind == Immediate && Imm.Type != ImmTyNone;
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}
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bool isDMask() const {
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return isImmTy(ImmTyDMask);
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}
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bool isUNorm() const { return isImmTy(ImmTyUNorm); }
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bool isDA() const { return isImmTy(ImmTyDA); }
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bool isR128() const { return isImmTy(ImmTyUNorm); }
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bool isLWE() const { return isImmTy(ImmTyLWE); }
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bool isMod() const {
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return isClamp() || isOMod();
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}
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@ -497,13 +519,17 @@ public:
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OperandMatchResultTy parseDMask(OperandVector &Operands);
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OperandMatchResultTy parseUNorm(OperandVector &Operands);
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OperandMatchResultTy parseDA(OperandVector &Operands);
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OperandMatchResultTy parseR128(OperandVector &Operands);
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OperandMatchResultTy parseLWE(OperandVector &Operands);
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void cvtId(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3_2_mod(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3_2_nomod(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3_only(MCInst &Inst, const OperandVector &Operands);
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void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
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void cvtMIMG(MCInst &Inst, const OperandVector &Operands);
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OperandMatchResultTy parseVOP3OptionalOps(OperandVector &Operands);
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};
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@ -1751,17 +1777,27 @@ void AMDGPUAsmParser::cvtMubuf(MCInst &Inst,
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseDMask(OperandVector &Operands) {
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return parseIntWithPrefix("dmask", Operands);
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return parseIntWithPrefix("dmask", Operands, AMDGPUOperand::ImmTyDMask);
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseUNorm(OperandVector &Operands) {
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return parseNamedBit("unorm", Operands);
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return parseNamedBit("unorm", Operands, AMDGPUOperand::ImmTyUNorm);
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseDA(OperandVector &Operands) {
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return parseNamedBit("da", Operands, AMDGPUOperand::ImmTyDA);
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseR128(OperandVector &Operands) {
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return parseNamedBit("r128", Operands);
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return parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128);
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseLWE(OperandVector &Operands) {
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return parseNamedBit("lwe", Operands, AMDGPUOperand::ImmTyLWE);
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}
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//===----------------------------------------------------------------------===//
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@ -1931,6 +1967,34 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
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}
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}
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void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) {
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OptionalImmIndexMap OptionalIdx;
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for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
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// Add the register arguments
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if (Op.isRegOrImm()) {
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Op.addRegOrImmOperands(Inst, 1);
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continue;
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} else if (Op.isImmModifier()) {
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OptionalIdx[Op.getImmTy()] = i;
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} else {
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assert(false);
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}
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}
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
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addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
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}
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/// Force static initialization.
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extern "C" void LLVMInitializeAMDGPUAsmParser() {
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RegisterMCAsmParser<AMDGPUAsmParser> A(TheAMDGPUTarget);
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@ -53,22 +53,25 @@ void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
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O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
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}
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void AMDGPUInstPrinter::printNamedBit(const MCInst* MI, unsigned OpNo, raw_ostream& O, const char* BitName) {
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if (MI->getOperand(OpNo).getImm()) {
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O << " " << BitName;
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}
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}
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void AMDGPUInstPrinter::printOffen(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " offen";
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printNamedBit(MI, OpNo, O, "offen");
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}
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void AMDGPUInstPrinter::printIdxen(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " idxen";
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printNamedBit(MI, OpNo, O, "idxen");
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}
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void AMDGPUInstPrinter::printAddr64(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " addr64";
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printNamedBit(MI, OpNo, O, "addr64");
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}
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void AMDGPUInstPrinter::printMBUFOffset(const MCInst *MI, unsigned OpNo,
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@ -106,26 +109,50 @@ void AMDGPUInstPrinter::printDSOffset1(const MCInst *MI, unsigned OpNo,
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void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " gds";
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printNamedBit(MI, OpNo, O, "gds");
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}
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void AMDGPUInstPrinter::printGLC(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " glc";
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printNamedBit(MI, OpNo, O, "glc");
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}
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void AMDGPUInstPrinter::printSLC(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " slc";
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printNamedBit(MI, OpNo, O, "slc");
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}
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void AMDGPUInstPrinter::printTFE(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm())
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O << " tfe";
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printNamedBit(MI, OpNo, O, "tfe");
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}
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void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).getImm()) {
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O << " dmask:";
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printU16ImmOperand(MI, OpNo, O);
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}
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}
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void AMDGPUInstPrinter::printUNorm(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printNamedBit(MI, OpNo, O, "unorm");
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}
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void AMDGPUInstPrinter::printDA(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printNamedBit(MI, OpNo, O, "da");
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}
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void AMDGPUInstPrinter::printR128(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printNamedBit(MI, OpNo, O, "r128");
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}
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void AMDGPUInstPrinter::printLWE(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printNamedBit(MI, OpNo, O, "lwe");
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}
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void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
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@ -38,6 +38,7 @@ private:
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void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printU32ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printNamedBit(const MCInst* MI, unsigned OpNo, raw_ostream& O, const char* BitName);
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void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printAddr64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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@ -49,6 +50,11 @@ private:
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void printGLC(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printSLC(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printTFE(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printDMask(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printUNorm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printDA(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printR128(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printLWE(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printRegOperand(unsigned RegNo, raw_ostream &O);
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void printVOPDst(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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void printImmediate32(uint32_t I, raw_ostream &O);
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@ -2657,7 +2657,8 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
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SelectionDAG &DAG) const {
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SDNode *Users[4] = { };
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unsigned Lane = 0;
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unsigned OldDmask = Node->getConstantOperandVal(0);
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unsigned DmaskIdx = (Node->getNumOperands() - Node->getNumValues() == 9) ? 2 : 3;
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unsigned OldDmask = Node->getConstantOperandVal(DmaskIdx);
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unsigned NewDmask = 0;
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// Try to figure out the used register components
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@ -2697,8 +2698,9 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
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// Adjust the writemask in the node
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std::vector<SDValue> Ops;
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Ops.insert(Ops.end(), Node->op_begin(), Node->op_begin() + DmaskIdx);
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Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
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Ops.insert(Ops.end(), Node->op_begin() + 1, Node->op_end());
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Ops.insert(Ops.end(), Node->op_begin() + DmaskIdx + 1, Node->op_end());
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Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
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// If we only got one lane, replace it with a copy
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@ -2796,7 +2798,8 @@ void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
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if (TII->isMIMG(*MI)) {
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unsigned VReg = MI->getOperand(0).getReg();
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unsigned Writemask = MI->getOperand(1).getImm();
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unsigned DmaskIdx = MI->getNumOperands() == 12 ? 3 : 4;
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unsigned Writemask = MI->getOperand(DmaskIdx).getImm();
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unsigned BitsSet = 0;
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for (unsigned i = 0; i < 4; ++i)
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BitsSet += Writemask & (1 << i) ? 1 : 0;
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@ -533,9 +533,30 @@ def SMRDLiteralOffsetMatchClass : SMRDOffsetBaseMatchClass <
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class OptionalImmAsmOperand <string OpName> : AsmOperandClass {
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let Name = "Imm"#OpName;
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let PredicateMethod = "isImm";
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let RenderMethod = "addImmOperands";
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let IsOptional = 1;
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}
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def DMaskMatchClass : AsmOperandClass {
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let Name = "DMask";
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let PredicateMethod = "isDMask";
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let ParserMethod = "parseDMask";
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let RenderMethod = "addImmOperands";
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let IsOptional = 1;
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}
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class NamedBitMatchClass<string BitName> : AsmOperandClass {
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let Name = "Imm"#BitName;
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let PredicateMethod = "is"#BitName;
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let ParserMethod = "parse"#BitName;
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let RenderMethod = "addImmOperands";
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let IsOptional = 1;
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}
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class NamedBitOperand<string BitName> : Operand<i1> {
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let PrintMethod = "print"#BitName;
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}
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let OperandType = "OPERAND_IMMEDIATE" in {
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def offen : Operand<i1> {
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@ -622,8 +643,30 @@ def smrd_literal_offset : Operand <i32> {
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let ParserMatchClass = SMRDLiteralOffsetMatchClass;
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}
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def dmask : Operand <i32> {
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let PrintMethod = "printDMask";
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let ParserMatchClass = DMaskMatchClass;
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}
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def unorm : NamedBitOperand<"UNorm"> {
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let ParserMatchClass = NamedBitMatchClass<"UNorm">;
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}
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def da : NamedBitOperand<"DA"> {
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let ParserMatchClass = NamedBitMatchClass<"DA">;
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}
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def r128 : NamedBitOperand<"R128"> {
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let ParserMatchClass = NamedBitMatchClass<"R128">;
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}
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def lwe : NamedBitOperand<"LWE"> {
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let ParserMatchClass = NamedBitMatchClass<"LWE">;
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}
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} // End OperandType = "OPERAND_IMMEDIATE"
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def VOPDstS64 : VOPDstOperand <SReg_64>;
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//===----------------------------------------------------------------------===//
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@ -2923,6 +2966,7 @@ class MIMG_Helper <bits<7> op, dag outs, dag ins, string asm,
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let hasPostISelHook = 1;
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let DecoderNamespace = dns;
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let isAsmParserOnly = !if(!eq(dns,""), 1, 0);
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let AsmMatchConverter = "cvtMIMG";
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}
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class MIMG_NoSampler_Helper <bits<7> op, string asm,
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@ -2931,11 +2975,10 @@ class MIMG_NoSampler_Helper <bits<7> op, string asm,
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string dns=""> : MIMG_Helper <
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op,
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(outs dst_rc:$vdata),
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(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, addr_rc:$vaddr,
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SReg_256:$srsrc),
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asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
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#" $tfe, $lwe, $slc, $vaddr, $srsrc",
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(ins addr_rc:$vaddr, SReg_256:$srsrc,
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dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc,
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r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
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asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da",
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dns> {
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let ssamp = 0;
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}
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@ -2964,11 +3007,11 @@ class MIMG_Store_Helper <bits<7> op, string asm,
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RegisterClass addr_rc> : MIMG_Helper <
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op,
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(outs),
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(ins data_rc:$vdata, i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, addr_rc:$vaddr,
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SReg_256:$srsrc),
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asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
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#" $tfe, $lwe, $slc, $vaddr, $srsrc"> {
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(ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
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dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc,
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r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
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asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
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> {
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let ssamp = 0;
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let mayLoad = 1; // TableGen requires this for matching with the intrinsics
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let mayStore = 1;
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@ -3001,11 +3044,10 @@ class MIMG_Sampler_Helper <bits<7> op, string asm,
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string dns=""> : MIMG_Helper <
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op,
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(outs dst_rc:$vdata),
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(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
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SReg_256:$srsrc, SReg_128:$ssamp),
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asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
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#" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
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(ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
|
||||
dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc,
|
||||
r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
|
||||
asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da",
|
||||
dns> {
|
||||
let WQM = wqm;
|
||||
}
|
||||
|
|
@ -3040,11 +3082,10 @@ class MIMG_Gather_Helper <bits<7> op, string asm,
|
|||
RegisterClass src_rc, int wqm> : MIMG <
|
||||
op,
|
||||
(outs dst_rc:$vdata),
|
||||
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
|
||||
i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr,
|
||||
SReg_256:$srsrc, SReg_128:$ssamp),
|
||||
asm#" $vdata, $dmask, $unorm, $glc, $da, $r128,"
|
||||
#" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp",
|
||||
(ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
|
||||
dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc,
|
||||
r128:$r128, tfe:$tfe, lwe:$lwe, da:$da),
|
||||
asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da",
|
||||
[]> {
|
||||
let mayLoad = 1;
|
||||
let mayStore = 0;
|
||||
|
|
|
|||
|
|
@ -2215,9 +2215,9 @@ def : Pat <
|
|||
class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm,
|
||||
i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe),
|
||||
(opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
|
||||
(as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
|
||||
$addr, $rsrc, $sampler)
|
||||
(opcode $addr, $rsrc, $sampler,
|
||||
(as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
|
||||
(as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da))
|
||||
>;
|
||||
|
||||
multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
|
||||
|
|
@ -2232,9 +2232,9 @@ multiclass SampleRawPatterns<SDPatternOperator name, string opcode> {
|
|||
class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm,
|
||||
imm:$r128, imm:$da, imm:$glc, imm:$slc, imm:$tfe, imm:$lwe),
|
||||
(opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da),
|
||||
(as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc),
|
||||
$addr, $rsrc)
|
||||
(opcode $addr, $rsrc,
|
||||
(as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc),
|
||||
(as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da))
|
||||
>;
|
||||
|
||||
multiclass ImagePatterns<SDPatternOperator name, string opcode> {
|
||||
|
|
@ -2246,8 +2246,9 @@ multiclass ImagePatterns<SDPatternOperator name, string opcode> {
|
|||
class ImageLoadPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$r128, imm:$da, imm:$glc,
|
||||
imm:$slc),
|
||||
(opcode (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $da),
|
||||
(as_i1imm $r128), 0, 0, (as_i1imm $slc), $addr, $rsrc)
|
||||
(opcode $addr, $rsrc,
|
||||
(as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
|
||||
(as_i1imm $r128), 0, 0, (as_i1imm $da))
|
||||
>;
|
||||
|
||||
multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> {
|
||||
|
|
@ -2259,8 +2260,9 @@ multiclass ImageLoadPatterns<SDPatternOperator name, string opcode> {
|
|||
class ImageStorePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name v4f32:$data, vt:$addr, v8i32:$rsrc, i32:$dmask, imm:$r128, imm:$da,
|
||||
imm:$glc, imm:$slc),
|
||||
(opcode $data, (as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $da),
|
||||
(as_i1imm $r128), 0, 0, (as_i1imm $slc), $addr, $rsrc)
|
||||
(opcode $data, $addr, $rsrc,
|
||||
(as_i32imm $dmask), 1, (as_i1imm $glc), (as_i1imm $slc),
|
||||
(as_i1imm $r128), 0, 0, (as_i1imm $da))
|
||||
>;
|
||||
|
||||
multiclass ImageStorePatterns<SDPatternOperator name, string opcode> {
|
||||
|
|
@ -2373,34 +2375,34 @@ defm : ImageStorePatterns<int_amdgcn_image_store_mip, "IMAGE_STORE_MIP">;
|
|||
/* SIsample for simple 1D texture lookup */
|
||||
def : Pat <
|
||||
(SIsample i32:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
|
||||
(IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
(IMAGE_SAMPLE_V4_V1 $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
|
||||
>;
|
||||
|
||||
class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, imm),
|
||||
(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
(opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
|
||||
>;
|
||||
|
||||
class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_RECT),
|
||||
(opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
(opcode $addr, $rsrc, $sampler, 0xf, 1, 0, 0, 0, 0, 0, 0)
|
||||
>;
|
||||
|
||||
class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat <
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_ARRAY),
|
||||
(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
(opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
|
||||
>;
|
||||
|
||||
class SampleShadowPattern<SDNode name, MIMG opcode,
|
||||
ValueType vt> : Pat <
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW),
|
||||
(opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
(opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 0)
|
||||
>;
|
||||
|
||||
class SampleShadowArrayPattern<SDNode name, MIMG opcode,
|
||||
ValueType vt> : Pat <
|
||||
(name vt:$addr, v8i32:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY),
|
||||
(opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler)
|
||||
(opcode $addr, $rsrc, $sampler, 0xf, 0, 0, 0, 0, 0, 0, 1)
|
||||
>;
|
||||
|
||||
/* SIsample* for texture lookups consuming more address parameters */
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_v2:
|
||||
;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_v2() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -15,7 +15,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4:
|
||||
;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -28,7 +28,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_cl:
|
||||
;CHECK: image_gather4_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -41,7 +41,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_l:
|
||||
;CHECK: image_gather4_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_l() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -54,7 +54,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_b:
|
||||
;CHECK: image_gather4_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_b() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -67,7 +67,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_b_cl:
|
||||
;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_b_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -80,7 +80,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_b_cl_v8:
|
||||
;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_b_cl_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -93,7 +93,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_lz_v2:
|
||||
;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_lz_v2() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -106,7 +106,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_lz:
|
||||
;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_lz() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -121,7 +121,7 @@ main_body:
|
|||
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_o:
|
||||
;CHECK: image_gather4_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -134,7 +134,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_cl_o:
|
||||
;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -147,7 +147,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_cl_o_v8:
|
||||
;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_cl_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -160,7 +160,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_l_o:
|
||||
;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_l_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -173,7 +173,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_l_o_v8:
|
||||
;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_l_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -186,7 +186,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_b_o:
|
||||
;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_b_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -199,7 +199,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_b_o_v8:
|
||||
;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_b_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -212,7 +212,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_b_cl_o:
|
||||
;CHECK: image_gather4_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_b_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -225,7 +225,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_lz_o:
|
||||
;CHECK: image_gather4_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_lz_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -240,7 +240,7 @@ main_body:
|
|||
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c:
|
||||
;CHECK: image_gather4_c {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -253,7 +253,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_cl:
|
||||
;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -266,7 +266,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_cl_v8:
|
||||
;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_cl_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -279,7 +279,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_l:
|
||||
;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_l() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -292,7 +292,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_l_v8:
|
||||
;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_l_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -305,7 +305,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_b:
|
||||
;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_b() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -318,7 +318,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_b_v8:
|
||||
;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_b_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -331,7 +331,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_b_cl:
|
||||
;CHECK: image_gather4_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_b_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -344,7 +344,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_lz:
|
||||
;CHECK: image_gather4_c_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_lz() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -359,7 +359,7 @@ main_body:
|
|||
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_o:
|
||||
;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -372,7 +372,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_o_v8:
|
||||
;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -385,7 +385,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_cl_o:
|
||||
;CHECK: image_gather4_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -398,7 +398,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_l_o:
|
||||
;CHECK: image_gather4_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_l_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -411,7 +411,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_b_o:
|
||||
;CHECK: image_gather4_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_b_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -424,7 +424,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_b_cl_o:
|
||||
;CHECK: image_gather4_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_b_cl_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -437,7 +437,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_lz_o:
|
||||
;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_lz_o() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -450,7 +450,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}gather4_c_lz_o_v8:
|
||||
;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da
|
||||
define void @gather4_c_lz_o_v8() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
|
||||
|
||||
;CHECK-LABEL: {{^}}getlod:
|
||||
;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x3 da
|
||||
define void @getlod() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.getlod.i32(i32 undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -13,7 +13,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}getlod_v2:
|
||||
;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x3 da
|
||||
define void @getlod_v2() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.getlod.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -24,7 +24,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}getlod_v4:
|
||||
;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x3 da
|
||||
define void @getlod_v4() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.getlod.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
|
||||
|
||||
;CHECK-LABEL: {{^}}image_load:
|
||||
;CHECK: image_load {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_load {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @image_load() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.load.v4i32(<4 x i32> undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -15,7 +15,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}image_load_mip:
|
||||
;CHECK: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @image_load_mip() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.load.mip.v4i32(<4 x i32> undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -28,7 +28,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}getresinfo:
|
||||
;CHECK: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @getresinfo() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.getresinfo.i32(i32 undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: {{^}}v1:
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 13
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xd
|
||||
define void @v1(i32 %a1) #0 {
|
||||
entry:
|
||||
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
|
||||
|
|
@ -15,7 +15,7 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}v2:
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 11
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xb
|
||||
define void @v2(i32 %a1) #0 {
|
||||
entry:
|
||||
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
|
||||
|
|
@ -28,7 +28,7 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}v3:
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 14
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xe
|
||||
define void @v3(i32 %a1) #0 {
|
||||
entry:
|
||||
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
|
||||
|
|
@ -41,7 +41,7 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}v4:
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 7
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x7
|
||||
define void @v4(i32 %a1) #0 {
|
||||
entry:
|
||||
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
|
||||
|
|
@ -54,7 +54,7 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}v5:
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 10
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xa
|
||||
define void @v5(i32 %a1) #0 {
|
||||
entry:
|
||||
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
|
||||
|
|
@ -66,7 +66,7 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}v6:
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 6
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x6
|
||||
define void @v6(i32 %a1) #0 {
|
||||
entry:
|
||||
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
|
||||
|
|
@ -78,7 +78,7 @@ entry:
|
|||
}
|
||||
|
||||
; CHECK-LABEL: {{^}}v7:
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 9
|
||||
; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x9
|
||||
define void @v7(i32 %a1) #0 {
|
||||
entry:
|
||||
%0 = insertelement <1 x i32> undef, i32 %a1, i32 0
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
;CHECK-LABEL: {{^}}sample:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -17,7 +17,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_cl:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -31,7 +31,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_d:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_d() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -45,7 +45,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_d_cl:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_d_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_d_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_d_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -59,7 +59,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_l:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_l {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_l() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -73,7 +73,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_b:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_b {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_b() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -87,7 +87,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_b_cl:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_b_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_b_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -101,7 +101,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_lz:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_lz {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_lz() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -115,7 +115,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_cd:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_cd {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_cd {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_cd() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -129,7 +129,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_cd_cl:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_cd_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_cd_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_cd_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -143,7 +143,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -157,7 +157,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_cl:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_c_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -171,7 +171,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_d:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_d() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -185,7 +185,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_d_cl:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_d_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_d_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_d_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -199,7 +199,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_l:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_l {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_l() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -213,7 +213,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_b:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_c_b {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_b() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -227,7 +227,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_b_cl:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_b_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -241,7 +241,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_lz:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_lz {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_lz() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -255,7 +255,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_cd:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_cd {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_cd {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_cd() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -269,7 +269,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_cd_cl:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_cd_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_cd_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_cd_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
;CHECK-LABEL: {{^}}sample:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -17,7 +17,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_cl:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -31,7 +31,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_d:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_d_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_d_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_d() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -45,7 +45,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_d_cl:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_d_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -59,7 +59,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_l:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_l_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_l() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -73,7 +73,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_b:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_b_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_b() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -87,7 +87,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_b_cl:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_b_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -101,7 +101,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_lz:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_lz_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_lz() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -115,7 +115,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_cd:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_cd_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_cd_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_cd() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -129,7 +129,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_cd_cl:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_cd_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -143,7 +143,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_c_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -157,7 +157,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_cl:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -171,7 +171,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_d:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_d_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_d_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_d() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -185,7 +185,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_d_cl:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_d_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -199,7 +199,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_l:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_l() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -213,7 +213,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_b:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_b() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -227,7 +227,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_b_cl:
|
||||
;CHECK: s_wqm
|
||||
;CHECK: image_sample_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_b_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -241,7 +241,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_lz:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_lz() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -255,7 +255,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_cd:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_cd_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_cd_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_cd() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
@ -269,7 +269,7 @@ main_body:
|
|||
|
||||
;CHECK-LABEL: {{^}}sample_c_cd_cl:
|
||||
;CHECK-NOT: s_wqm
|
||||
;CHECK: image_sample_c_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}
|
||||
;CHECK: image_sample_c_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf
|
||||
define void @sample_c_cd_cl() #0 {
|
||||
main_body:
|
||||
%r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
|
||||
|
||||
;CHECK-LABEL: {{^}}image_load_v4i32:
|
||||
;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[0:3], s[0:7]
|
||||
;CHECK: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm
|
||||
;CHECK: s_waitcnt vmcnt(0)
|
||||
define <4 x float> @image_load_v4i32(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
|
||||
main_body:
|
||||
|
|
@ -11,7 +11,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}image_load_v2i32:
|
||||
;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[0:1], s[0:7]
|
||||
;CHECK: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm
|
||||
;CHECK: s_waitcnt vmcnt(0)
|
||||
define <4 x float> @image_load_v2i32(<8 x i32> inreg %rsrc, <2 x i32> %c) #0 {
|
||||
main_body:
|
||||
|
|
@ -20,7 +20,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}image_load_i32:
|
||||
;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v0, s[0:7]
|
||||
;CHECK: image_load v[0:3], v0, s[0:7] dmask:0xf unorm
|
||||
;CHECK: s_waitcnt vmcnt(0)
|
||||
define <4 x float> @image_load_i32(<8 x i32> inreg %rsrc, i32 %c) #0 {
|
||||
main_body:
|
||||
|
|
@ -29,7 +29,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}image_load_mip:
|
||||
;CHECK: image_load_mip v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[0:3], s[0:7]
|
||||
;CHECK: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm
|
||||
;CHECK: s_waitcnt vmcnt(0)
|
||||
define <4 x float> @image_load_mip(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
|
||||
main_body:
|
||||
|
|
@ -38,7 +38,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}image_load_1:
|
||||
;CHECK: image_load v0, 1, -1, 0, 0, 0, 0, 0, 0, v[0:3], s[0:7]
|
||||
;CHECK: image_load v0, v[0:3], s[0:7] dmask:0x1 unorm
|
||||
;CHECK: s_waitcnt vmcnt(0)
|
||||
define float @image_load_1(<8 x i32> inreg %rsrc, <4 x i32> %c) #0 {
|
||||
main_body:
|
||||
|
|
@ -49,7 +49,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}image_store_v4i32:
|
||||
;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[4:7], s[0:7]
|
||||
;CHECK: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm
|
||||
define void @image_store_v4i32(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) #0 {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
|
||||
|
|
@ -57,7 +57,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}image_store_v2i32:
|
||||
;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[4:5], s[0:7]
|
||||
;CHECK: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm
|
||||
define void @image_store_v2i32(<8 x i32> inreg %rsrc, <4 x float> %data, <2 x i32> %coords) #0 {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.v2i32(<4 x float> %data, <2 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
|
||||
|
|
@ -65,7 +65,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}image_store_i32:
|
||||
;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[0:7]
|
||||
;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm
|
||||
define void @image_store_i32(<8 x i32> inreg %rsrc, <4 x float> %data, i32 %coords) #0 {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
|
||||
|
|
@ -73,7 +73,7 @@ main_body:
|
|||
}
|
||||
|
||||
;CHECK-LABEL: {{^}}image_store_mip:
|
||||
;CHECK: image_store_mip v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v[4:7], s[0:7]
|
||||
;CHECK: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm
|
||||
define void @image_store_mip(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) #0 {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.mip.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
|
||||
|
|
@ -83,11 +83,11 @@ main_body:
|
|||
; Ideally, the register allocator would avoid the wait here
|
||||
;
|
||||
;CHECK-LABEL: {{^}}image_store_wait:
|
||||
;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[0:7]
|
||||
;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm
|
||||
;CHECK: s_waitcnt vmcnt(0) expcnt(0)
|
||||
;CHECK: image_load v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[8:15]
|
||||
;CHECK: image_load v[0:3], v4, s[8:15] dmask:0xf unorm
|
||||
;CHECK: s_waitcnt vmcnt(0)
|
||||
;CHECK: image_store v[0:3], 15, -1, 0, 0, 0, 0, 0, 0, v4, s[16:23]
|
||||
;CHECK: image_store v[0:3], v4, s[16:23] dmask:0xf unorm
|
||||
define void @image_store_wait(<8 x i32> inreg, <8 x i32> inreg, <8 x i32> inreg, <4 x float>, i32) #0 {
|
||||
main_body:
|
||||
call void @llvm.amdgcn.image.store.i32(<4 x float> %3, i32 %4, <8 x i32> %0, i32 15, i1 0, i1 0, i1 0, i1 0)
|
||||
|
|
|
|||
|
|
@ -364,7 +364,7 @@ bb71: ; preds = %bb80, %bb38
|
|||
|
||||
; Check the the resource descriptor is stored in an sgpr.
|
||||
; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:
|
||||
; CHECK: image_sample v{{[0-9]+}}, 1, 0, 0, 0, 0, 0, 0, 0, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
|
||||
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
|
||||
define void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
|
||||
%tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i32 0, i32 %tid
|
||||
|
|
@ -379,7 +379,7 @@ define void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
|
|||
|
||||
; Check the the sampler is stored in an sgpr.
|
||||
; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:
|
||||
; CHECK: image_sample v{{[0-9]+}}, 1, 0, 0, 0, 0, 0, 0, 0, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
|
||||
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
|
||||
define void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
|
||||
%tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i32 0, i32 %tid
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
; the wrong register class is used for the REG_SEQUENCE instructions.
|
||||
|
||||
; CHECK: {{^}}main:
|
||||
; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, 15, 0, 0, 0, 0, 0, 0, 0, v{{\[[0-9]:[0-9]\]}}
|
||||
; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, v{{\[[0-9]:[0-9]\]}}, s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0xf
|
||||
define void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
|
||||
main_body:
|
||||
%tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
; Make sure that when we split an smrd instruction in order to move it to
|
||||
; the VALU, we are also moving its users to the VALU.
|
||||
; CHECK-LABEL: {{^}}split_smrd_add_worklist:
|
||||
; CHECK: image_sample v{{[0-9]+}}, 1, 0, 0, 0, 0, 0, 0, 0, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
|
||||
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
|
||||
|
||||
define void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(2)* byval %arg) #0 {
|
||||
bb:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,15 @@
|
|||
// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=SICI
|
||||
// RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
|
||||
|
||||
image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm
|
||||
// SICI: image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0xed,0x04,0x07,0x00]
|
||||
// VI: image_load v[4:6], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x00,0xf0,0xed,0x04,0x07,0x00]
|
||||
|
||||
image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm
|
||||
// SICI: image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
|
||||
// VI : image_store v[193:195], v[237:240], s[28:35] dmask:0x7 unorm ; encoding: [0x00,0x17,0x20,0xf0,0xed,0xc1,0x07,0x00]
|
||||
|
||||
image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm
|
||||
// SICI: image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm ; encoding: [0x00,0x17,0x80,0xf0,0xed,0xc1,0x27,0x00]
|
||||
// VI : image_sample v[193:195], v[237:240], s[28:35], s[4:7] dmask:0x7 unorm ; encoding: [0x00,0x17,0x80,0xf0,0xed,0xc1,0x27,0x00]
|
||||
Loading…
Reference in New Issue