forked from OSchip/llvm-project
Fix bug codegen'ing FP constant vectors with integer splats. Make sure the
created intrinsics have the right integer types. This fixes PowerPC/2006-11-29-AltivecFPSplat.ll llvm-svn: 32024
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c386b40714
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2f648fc55d
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@ -1973,6 +1973,7 @@ static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
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Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
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SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
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&Ops[0], Ops.size());
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if (VT == MVT::Other) return Res;
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return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
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}
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@ -2086,6 +2087,7 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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-1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
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-8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
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};
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for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
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// Indirect through the SplatCsts array so that we favor 'vsplti -1' for
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// cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
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@ -2097,43 +2099,47 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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// vsplti + shl self.
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if (SextVal == (i << (int)TypeShiftAmt)) {
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Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
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SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
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Intrinsic::ppc_altivec_vslw
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};
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return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
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return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
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}
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// vsplti + srl self.
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if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
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Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
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SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
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Intrinsic::ppc_altivec_vsrw
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};
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return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
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return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
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}
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// vsplti + sra self.
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if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
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Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
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SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
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Intrinsic::ppc_altivec_vsraw
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};
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return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
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return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
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}
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// vsplti + rol self.
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if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
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((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
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Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
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SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
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static const unsigned IIDs[] = { // Intrinsic to use for each size.
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Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
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Intrinsic::ppc_altivec_vrlw
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};
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return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
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Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
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return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
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}
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// t = vsplti c, result = vsldoi t, t, 1
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@ -2157,15 +2163,17 @@ static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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// Odd, in range [17,31]: (vsplti C)-(vsplti -16).
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if (SextVal >= 0 && SextVal <= 31) {
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SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
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SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
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return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
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SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
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SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
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LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
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return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
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}
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// Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
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if (SextVal >= -31 && SextVal <= 0) {
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SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
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SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
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return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
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SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
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SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
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LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
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return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
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}
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}
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