diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 9bff61e3460e..565c02c6acd1 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -851,6 +851,9 @@ def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), // Additional Altivec Patterns // +// Extended mnemonics +def : InstAlias<"vmr $vD, $vA", (VOR vrrc:$vD, vrrc:$vA, vrrc:$vA)>; + // Loads. def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>; diff --git a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll index f2b8e09a1c1d..b7beb8165fdf 100644 --- a/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll +++ b/llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll @@ -859,7 +859,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -876,7 +876,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -893,7 +893,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -910,7 +910,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -927,9 +927,9 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bc 12, [[REG1]], .LBB[[BB1:[0-9_]+]] -; CHECK: vor 3, 2, 2 +; CHECK: vmr 3, 2 ; CHECK: .LBB[[BB1]] -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -946,7 +946,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -963,7 +963,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -980,7 +980,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -997,7 +997,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1014,7 +1014,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1062,7 +1062,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1079,7 +1079,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1096,7 +1096,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1113,7 +1113,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1130,9 +1130,9 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bc 12, [[REG1]], .LBB[[BB55:[0-9_]+]] -; CHECK: vor 3, 2, 2 +; CHECK: vmr 3, 2 ; CHECK: .LBB[[BB55]] -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1149,7 +1149,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1166,7 +1166,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1183,7 +1183,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1200,7 +1200,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } @@ -1217,7 +1217,7 @@ entry: ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: bclr 12, [[REG1]], 0 -; CHECK: vor 2, 3, 3 +; CHECK: vmr 2, 3 ; CHECK: blr } diff --git a/llvm/test/CodeGen/PowerPC/vsx-args.ll b/llvm/test/CodeGen/PowerPC/vsx-args.ll index 252f9b360b96..7fa31aea84ba 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-args.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-args.ll @@ -13,10 +13,10 @@ entry: ret <2 x double> %v ; CHECK-LABEL: @main -; CHECK-DAG: vor [[V:[0-9]+]], 2, 2 -; CHECK-DAG: vor 2, 3, 3 -; CHECK-DAG: vor 3, 4, 4 -; CHECK-DAG: vor 4, [[V]], [[V]] +; CHECK-DAG: vmr [[V:[0-9]+]], 2 +; CHECK-DAG: vmr 2, 3 +; CHECK-DAG: vmr 3, 4 +; CHECK-DAG: vmr 4, [[V]] ; CHECK: bl sv ; CHECK: lxvd2x [[VC:[0-9]+]], ; CHECK: xvadddp 34, 34, [[VC]] @@ -24,8 +24,8 @@ entry: ; CHECK-FISL-LABEL: @main ; CHECK-FISL: stxvd2x 34 -; CHECK-FISL: vor 2, 3, 3 -; CHECK-FISL: vor 3, 4, 4 +; CHECK-FISL: vmr 2, 3 +; CHECK-FISL: vmr 3, 4 ; CHECK-FISL: lxvd2x 36 ; CHECK-FISL: bl sv ; CHECK-FISL: lxvd2x [[VC:[0-9]+]], diff --git a/llvm/test/CodeGen/PowerPC/vsx-infl-copy1.ll b/llvm/test/CodeGen/PowerPC/vsx-infl-copy1.ll index 592f85e2bcaf..1d6718279a0d 100644 --- a/llvm/test/CodeGen/PowerPC/vsx-infl-copy1.ll +++ b/llvm/test/CodeGen/PowerPC/vsx-infl-copy1.ll @@ -11,15 +11,15 @@ entry: br label %vector.body ; CHECK-LABEL: @_Z8example9Pj -; CHECK: vor -; CHECK: vor -; CHECK: vor -; CHECK: vor -; CHECK: vor -; CHECK: vor -; CHECK: vor -; CHECK: vor -; CHECK: vor +; CHECK: vmr +; CHECK: vmr +; CHECK: vmr +; CHECK: vmr +; CHECK: vmr +; CHECK: vmr +; CHECK: vmr +; CHECK: vmr +; CHECK: vmr vector.body: ; preds = %vector.body, %entry %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s b/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s index 16c48a71e428..bc595a54dc4a 100644 --- a/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s +++ b/llvm/test/MC/PowerPC/ppc64-encoding-vmx.s @@ -553,6 +553,9 @@ # CHECK-BE: vor 2, 3, 4 # encoding: [0x10,0x43,0x24,0x84] # CHECK-LE: vor 2, 3, 4 # encoding: [0x84,0x24,0x43,0x10] vor 2, 3, 4 +# CHECK-BE: vmr 2, 3 # encoding: [0x10,0x43,0x1c,0x84] +# CHECK-LE: vmr 2, 3 # encoding: [0x84,0x1c,0x43,0x10] + vmr 2, 3 # CHECK-BE: vxor 2, 3, 4 # encoding: [0x10,0x43,0x24,0xc4] # CHECK-LE: vxor 2, 3, 4 # encoding: [0xc4,0x24,0x43,0x10] vxor 2, 3, 4