forked from OSchip/llvm-project
parent
116b305d31
commit
2f14b0bb1d
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@ -11,6 +11,9 @@
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let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.".
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// Miscellaneous instructions.
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def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>;
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def int_xcore_crc8 : Intrinsic<[llvm_i32_ty, llvm_i32_ty],
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[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
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[IntrNoMem]>;
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def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrNoMem]>;
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def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
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def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;
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@ -205,6 +205,16 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode *N) {
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return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32,
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Ops, 4);
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}
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
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switch (IntNo) {
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case Intrinsic::xcore_crc8:
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SDValue Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3) };
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return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32,
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Ops, 3);
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}
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break;
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}
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case ISD::BRIND:
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if (SDNode *ResNode = SelectBRIND(N))
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return ResNode;
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@ -504,6 +504,12 @@ def MACCS_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
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[]>;
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}
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let Constraints = "$src1 = $dst1" in
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def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
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"crc8 $dst1, $dst2, $src2, $src3",
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[]>;
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// Five operand long
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def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
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@ -1,6 +1,9 @@
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; RUN: llc < %s -march=xcore | FileCheck %s
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%0 = type { i32, i32 }
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declare i32 @llvm.xcore.bitrev(i32)
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declare i32 @llvm.xcore.crc32(i32, i32, i32)
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declare %0 @llvm.xcore.crc8(i32, i32, i32)
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define i32 @bitrev(i32 %val) {
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; CHECK: bitrev:
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@ -15,3 +18,10 @@ define i32 @crc32(i32 %crc, i32 %data, i32 %poly) {
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%result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly)
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ret i32 %result
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}
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define %0 @crc8(i32 %crc, i32 %data, i32 %poly) {
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; CHECK: crc8:
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; CHECK: crc8 r0, r1, r1, r2
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%result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly)
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ret %0 %result
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}
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