forked from OSchip/llvm-project
[AMDGPU][MC] Corrected parsing of FLAT offset modifier
Summary of changes: - simplified handling of FLAT offset: offset_s13 and offset_u12 have been replaced with flat_offset; - provided information about error position for pre-gfx9 targets; - improved errors handling. Reviewers: artem.tamazov, arsenm, rampitec Differential Revision: https://reviews.llvm.org/D64244 llvm-svn: 365321
This commit is contained in:
Dmitry Preobrazhensky
parent
bd791b57f8
commit
2eff0318c6
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@ -316,8 +316,7 @@ public:
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bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }
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bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }
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bool isOffsetU12() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isUInt<12>(getImm()); }
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bool isOffsetS13() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isInt<13>(getImm()); }
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bool isFlatOffset() const { return isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset); }
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bool isGDS() const { return isImmTy(ImmTyGDS); }
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bool isLDS() const { return isImmTy(ImmTyLDS); }
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bool isDLC() const { return isImmTy(ImmTyDLC); }
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@ -1154,15 +1153,17 @@ private:
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const SMLoc Loc);
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bool parseHwregBody(OperandInfoTy &HwReg, int64_t &Offset, int64_t &Width);
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void validateHwreg(const OperandInfoTy &HwReg,
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bool validateHwreg(const OperandInfoTy &HwReg,
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const int64_t Offset,
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const int64_t Width,
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const SMLoc Loc);
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void errorExpTgt();
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OperandMatchResultTy parseExpTgtImpl(StringRef Str, uint8_t &Val);
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SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;
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bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc);
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bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
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bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
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bool validateSOPLiteral(const MCInst &Inst) const;
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bool validateConstantBusLimitations(const MCInst &Inst);
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bool validateEarlyClobberLimitations(const MCInst &Inst);
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@ -1238,8 +1239,7 @@ public:
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AMDGPUOperand::Ptr defaultSMRDOffset8() const;
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AMDGPUOperand::Ptr defaultSMRDOffset20() const;
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AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
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AMDGPUOperand::Ptr defaultOffsetU12() const;
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AMDGPUOperand::Ptr defaultOffsetS13() const;
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AMDGPUOperand::Ptr defaultFlatOffset() const;
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OperandMatchResultTy parseOModOperand(OperandVector &Operands);
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@ -2437,28 +2437,6 @@ unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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}
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}
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if (TSFlags & SIInstrFlags::FLAT) {
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// FIXME: Produces error without correct column reported.
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auto Opcode = Inst.getOpcode();
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auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);
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const auto &Op = Inst.getOperand(OpNum);
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if (!hasFlatOffsets() && Op.getImm() != 0)
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return Match_InvalidOperand;
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// GFX10: Address offset is 12-bit signed byte offset. Must be positive for
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// FLAT segment. For FLAT segment MSB is ignored and forced to zero.
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if (isGFX10()) {
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if (TSFlags & SIInstrFlags::IsNonFlatSeg) {
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if (!isInt<12>(Op.getImm()))
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return Match_InvalidOperand;
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} else {
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if (!isUInt<11>(Op.getImm()))
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return Match_InvalidOperand;
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}
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}
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}
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return Match_Success;
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}
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@ -3007,6 +2985,55 @@ bool AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
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return (Desc.TSFlags & SIInstrFlags::SDWA) == 0 && !IsRevOpcode(Opcode);
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}
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SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {
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for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
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AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
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if (Op.isFlatOffset())
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return Op.getStartLoc();
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}
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return getLoc();
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}
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bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,
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const OperandVector &Operands) {
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uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
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if ((TSFlags & SIInstrFlags::FLAT) == 0)
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return true;
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auto Opcode = Inst.getOpcode();
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auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);
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assert(OpNum != -1);
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const auto &Op = Inst.getOperand(OpNum);
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if (!hasFlatOffsets() && Op.getImm() != 0) {
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Error(getFlatOffsetLoc(Operands),
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"flat offset modifier is not supported on this GPU");
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return false;
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}
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// Address offset is 12-bit signed for GFX10, 13-bit for GFX9.
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// For FLAT segment the offset must be positive;
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// MSB is ignored and forced to zero.
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unsigned OffsetSize = isGFX9() ? 13 : 12;
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if (TSFlags & SIInstrFlags::IsNonFlatSeg) {
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if (!isIntN(OffsetSize, Op.getImm())) {
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Error(getFlatOffsetLoc(Operands),
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isGFX9() ? "expected a 13-bit signed offset" :
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"expected a 12-bit signed offset");
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return false;
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}
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} else {
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if (!isUIntN(OffsetSize - 1, Op.getImm())) {
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Error(getFlatOffsetLoc(Operands),
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isGFX9() ? "expected a 12-bit unsigned offset" :
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"expected an 11-bit unsigned offset");
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return false;
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}
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}
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return true;
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}
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bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
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unsigned Opcode = Inst.getOpcode();
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const MCInstrDesc &Desc = MII.get(Opcode);
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@ -3097,7 +3124,8 @@ bool AMDGPUAsmParser::validateVOP3Literal(const MCInst &Inst) const {
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}
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bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
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const SMLoc &IDLoc) {
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const SMLoc &IDLoc,
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const OperandVector &Operands) {
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if (!validateLdsDirect(Inst)) {
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Error(IDLoc,
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"invalid use of lds_direct");
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@ -3163,6 +3191,9 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
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"invalid image_gather dmask: only one bit must be set");
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return false;
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}
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if (!validateFlatOffset(Inst, Operands)) {
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return false;
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}
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return true;
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}
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@ -3203,7 +3234,7 @@ bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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switch (Result) {
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default: break;
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case Match_Success:
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if (!validateInstruction(Inst, IDLoc)) {
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if (!validateInstruction(Inst, IDLoc, Operands)) {
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return true;
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}
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Inst.setLoc(IDLoc);
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@ -4658,7 +4689,7 @@ AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg,
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skipToken(AsmToken::RParen, "expected a closing parenthesis");
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}
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void
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bool
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AMDGPUAsmParser::validateHwreg(const OperandInfoTy &HwReg,
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const int64_t Offset,
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const int64_t Width,
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@ -4668,13 +4699,18 @@ AMDGPUAsmParser::validateHwreg(const OperandInfoTy &HwReg,
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if (HwReg.IsSymbolic && !isValidHwreg(HwReg.Id, getSTI())) {
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Error(Loc, "specified hardware register is not supported on this GPU");
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return false;
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} else if (!isValidHwreg(HwReg.Id)) {
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Error(Loc, "invalid code of hardware register: only 6-bit values are legal");
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return false;
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} else if (!isValidHwregOffset(Offset)) {
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Error(Loc, "invalid bit offset: only 5-bit values are legal");
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return false;
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} else if (!isValidHwregWidth(Width)) {
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Error(Loc, "invalid bitfield width: only values from 1 to 32 are legal");
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return false;
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}
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return true;
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}
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OperandMatchResultTy
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@ -4690,8 +4726,8 @@ AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
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OperandInfoTy HwReg(ID_UNKNOWN_);
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int64_t Offset = OFFSET_DEFAULT_;
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int64_t Width = WIDTH_DEFAULT_;
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if (parseHwregBody(HwReg, Offset, Width)) {
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validateHwreg(HwReg, Offset, Width, Loc);
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if (parseHwregBody(HwReg, Offset, Width) &&
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validateHwreg(HwReg, Offset, Width, Loc)) {
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ImmVal = encodeHwreg(HwReg.Id, Offset, Width);
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}
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} else if (parseExpr(ImmVal)) {
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@ -5646,11 +5682,7 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defaultSMRDLiteralOffset() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
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}
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AMDGPUOperand::Ptr AMDGPUAsmParser::defaultOffsetU12() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
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}
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AMDGPUOperand::Ptr AMDGPUAsmParser::defaultOffsetS13() const {
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AMDGPUOperand::Ptr AMDGPUAsmParser::defaultFlatOffset() const {
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return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
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}
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@ -135,17 +135,15 @@ class GlobalSaddrTable <bit is_saddr, string Name = ""> {
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// saddr is 32-bit (which isn't handled here yet).
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class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
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bit HasTiedOutput = 0,
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bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
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bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
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opName,
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(outs regClass:$vdst),
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!con(
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!con(
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!con(
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!con((ins VReg_64:$vaddr),
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!if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
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(ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)),
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(ins GLC:$glc, SLC:$slc, DLC:$dlc)),
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!if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
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!con((ins VReg_64:$vaddr),
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!if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
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(ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
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!if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
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" $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
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let has_data = 0;
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let mayLoad = 1;
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@ -159,15 +157,13 @@ class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
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}
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class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
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bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
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bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
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opName,
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(outs),
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!con(
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!con(
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!con((ins VReg_64:$vaddr, vdataClass:$vdata),
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!if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
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(ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)),
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(ins GLC:$glc, SLC:$slc, DLC:$dlc)),
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!con((ins VReg_64:$vaddr, vdataClass:$vdata),
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!if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
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(ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
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" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
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let mayLoad = 0;
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let mayStore = 1;
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@ -180,18 +176,18 @@ class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
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multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
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let is_flat_global = 1 in {
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def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1, 1>,
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def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1>,
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GlobalSaddrTable<0, opName>;
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def _SADDR : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1, 1, 1>,
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def _SADDR : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1, 1>,
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GlobalSaddrTable<1, opName>;
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}
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}
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multiclass FLAT_Global_Store_Pseudo<string opName, RegisterClass regClass> {
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let is_flat_global = 1 in {
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def "" : FLAT_Store_Pseudo<opName, regClass, 1, 1>,
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def "" : FLAT_Store_Pseudo<opName, regClass, 1>,
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GlobalSaddrTable<0, opName>;
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def _SADDR : FLAT_Store_Pseudo<opName, regClass, 1, 1, 1>,
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def _SADDR : FLAT_Store_Pseudo<opName, regClass, 1, 1>,
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GlobalSaddrTable<1, opName>;
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}
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}
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@ -201,8 +197,8 @@ class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
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opName,
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(outs regClass:$vdst),
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!if(EnableSaddr,
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(ins SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
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(ins VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
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(ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
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(ins VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
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" $vdst, "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc$dlc"> {
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let has_data = 0;
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let mayLoad = 1;
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@ -217,8 +213,8 @@ class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit En
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opName,
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(outs),
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!if(EnableSaddr,
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(ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
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(ins vdataClass:$vdata, VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
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(ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
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(ins vdataClass:$vdata, VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
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" "#!if(EnableSaddr, "off", "$vaddr")#", $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$glc$slc$dlc"> {
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let mayLoad = 0;
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let mayStore = 1;
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@ -277,7 +273,7 @@ multiclass FLAT_Atomic_Pseudo<
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bit isFP = getIsFP<data_vt>.ret> {
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def "" : FLAT_AtomicNoRet_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, SLC:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc),
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" $vaddr, $vdata$offset$slc">,
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GlobalSaddrTable<0, opName>,
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AtomicNoRet <opName, 0> {
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@ -287,7 +283,7 @@ multiclass FLAT_Atomic_Pseudo<
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def _RTN : FLAT_AtomicRet_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, SLC:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc),
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" $vdst, $vaddr, $vdata$offset glc$slc",
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[(set vt:$vdst,
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(atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
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@ -308,7 +304,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
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def "" : FLAT_AtomicNoRet_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, SLC:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc),
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" $vaddr, $vdata, off$offset$slc">,
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GlobalSaddrTable<0, opName>,
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AtomicNoRet <opName, 0> {
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@ -319,7 +315,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_RTN<
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def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
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(outs),
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(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, SLC:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, flat_offset:$offset, SLC:$slc),
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" $vaddr, $vdata, $saddr$offset$slc">,
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GlobalSaddrTable<1, opName>,
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AtomicNoRet <opName#"_saddr", 0> {
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@ -341,7 +337,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
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def _RTN : FLAT_AtomicRet_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, SLC:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc),
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" $vdst, $vaddr, $vdata, off$offset glc$slc",
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[(set vt:$vdst,
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(atomic (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
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@ -353,7 +349,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN<
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def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
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(outs vdst_rc:$vdst),
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(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, SLC:$slc),
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(ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, flat_offset:$offset, SLC:$slc),
|
||||
" $vdst, $vaddr, $vdata, $saddr$offset glc$slc">,
|
||||
GlobalSaddrTable<1, opName#"_rtn">,
|
||||
AtomicNoRet <opName#"_saddr", 1> {
|
||||
|
|
|
|||
|
|
@ -71,17 +71,6 @@ void AMDGPUInstPrinter::printU16ImmDecOperand(const MCInst *MI, unsigned OpNo,
|
|||
O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
|
||||
}
|
||||
|
||||
void AMDGPUInstPrinter::printS13ImmDecOperand(const MCInst *MI, unsigned OpNo,
|
||||
const MCSubtargetInfo &STI,
|
||||
raw_ostream &O) {
|
||||
// GFX10: Address offset is 12-bit signed byte offset.
|
||||
if (AMDGPU::isGFX10(STI)) {
|
||||
O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
|
||||
} else {
|
||||
O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
|
||||
}
|
||||
}
|
||||
|
||||
void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
|
||||
const MCSubtargetInfo &STI,
|
||||
raw_ostream &O) {
|
||||
|
|
@ -128,13 +117,25 @@ void AMDGPUInstPrinter::printOffset(const MCInst *MI, unsigned OpNo,
|
|||
}
|
||||
}
|
||||
|
||||
void AMDGPUInstPrinter::printOffsetS13(const MCInst *MI, unsigned OpNo,
|
||||
const MCSubtargetInfo &STI,
|
||||
raw_ostream &O) {
|
||||
void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
|
||||
const MCSubtargetInfo &STI,
|
||||
raw_ostream &O) {
|
||||
uint16_t Imm = MI->getOperand(OpNo).getImm();
|
||||
if (Imm != 0) {
|
||||
O << ((OpNo == 0)? "offset:" : " offset:");
|
||||
printS13ImmDecOperand(MI, OpNo, STI, O);
|
||||
|
||||
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
|
||||
bool IsFlatSeg = !(Desc.TSFlags & SIInstrFlags::IsNonFlatSeg);
|
||||
|
||||
if (IsFlatSeg) { // Unsigned offset
|
||||
printU16ImmDecOperand(MI, OpNo, O);
|
||||
} else { // Signed offset
|
||||
if (AMDGPU::isGFX10(STI)) {
|
||||
O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
|
||||
} else {
|
||||
O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -41,8 +41,6 @@ private:
|
|||
void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printS13ImmDecOperand(const MCInst *MI, unsigned OpNo,
|
||||
const MCSubtargetInfo &STI, raw_ostream &O);
|
||||
void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
|
||||
const MCSubtargetInfo &STI, raw_ostream &O);
|
||||
void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O,
|
||||
|
|
@ -53,8 +51,8 @@ private:
|
|||
void printMBUFOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
|
||||
void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
void printOffsetS13(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
|
||||
void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
|
||||
raw_ostream &O);
|
||||
|
|
|
|||
|
|
@ -844,21 +844,11 @@ class NamedOperandU8<string Name, AsmOperandClass MatchClass> : Operand<i8> {
|
|||
let ParserMatchClass = MatchClass;
|
||||
}
|
||||
|
||||
class NamedOperandU12<string Name, AsmOperandClass MatchClass> : Operand<i16> {
|
||||
let PrintMethod = "print"#Name;
|
||||
let ParserMatchClass = MatchClass;
|
||||
}
|
||||
|
||||
class NamedOperandU16<string Name, AsmOperandClass MatchClass> : Operand<i16> {
|
||||
let PrintMethod = "print"#Name;
|
||||
let ParserMatchClass = MatchClass;
|
||||
}
|
||||
|
||||
class NamedOperandS13<string Name, AsmOperandClass MatchClass> : Operand<i16> {
|
||||
let PrintMethod = "print"#Name;
|
||||
let ParserMatchClass = MatchClass;
|
||||
}
|
||||
|
||||
class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
|
||||
let PrintMethod = "print"#Name;
|
||||
let ParserMatchClass = MatchClass;
|
||||
|
|
@ -876,8 +866,7 @@ def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>;
|
|||
def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>;
|
||||
def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>;
|
||||
|
||||
def offset_u12 : NamedOperandU12<"Offset", NamedMatchClass<"OffsetU12">>;
|
||||
def offset_s13 : NamedOperandS13<"OffsetS13", NamedMatchClass<"OffsetS13">>;
|
||||
def flat_offset : NamedOperandU16<"FlatOffset", NamedMatchClass<"FlatOffset">>;
|
||||
def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>;
|
||||
def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
|
||||
def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
|
||||
|
|
|
|||
|
|
@ -694,7 +694,7 @@ bool isValidHwregWidth(int64_t Width) {
|
|||
return 0 <= (Width - 1) && isUInt<WIDTH_M1_WIDTH_>(Width - 1);
|
||||
}
|
||||
|
||||
int64_t encodeHwreg(int64_t Id, int64_t Offset, int64_t Width) {
|
||||
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width) {
|
||||
return (Id << ID_SHIFT_) |
|
||||
(Offset << OFFSET_SHIFT_) |
|
||||
((Width - 1) << WIDTH_M1_SHIFT_);
|
||||
|
|
|
|||
|
|
@ -439,7 +439,7 @@ LLVM_READNONE
|
|||
bool isValidHwregWidth(int64_t Width);
|
||||
|
||||
LLVM_READNONE
|
||||
int64_t encodeHwreg(int64_t Id, int64_t Offset, int64_t Width);
|
||||
uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
|
||||
|
||||
LLVM_READNONE
|
||||
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
|
||||
|
|
|
|||
|
|
@ -5,13 +5,13 @@ flat_load_dword v1, v[3:4]
|
|||
// GFX10: encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x7d,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:-1
|
||||
// GFX10-ERR: error: invalid operand for instruction
|
||||
// GFX10-ERR: :28: error: expected an 11-bit unsigned offset
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:2047
|
||||
// GFX10: encoding: [0xff,0x07,0x30,0xdc,0x03,0x00,0x7d,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:2048
|
||||
// GFX10-ERR: error: invalid operand for instruction
|
||||
// GFX10-ERR: error: expected an 11-bit unsigned offset
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:4 glc
|
||||
// GFX10: encoding: [0x04,0x00,0x31,0xdc,0x03,0x00,0x7d,0x01]
|
||||
|
|
|
|||
|
|
@ -9,39 +9,41 @@ flat_load_dword v1, v[3:4] offset:0
|
|||
// GCN: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:-1
|
||||
// GCN-ERR: :35: error: failed parsing operand.
|
||||
// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
|
||||
// GFX9-ERR: :28: error: expected a 12-bit unsigned offset
|
||||
|
||||
// FIXME: Error on VI in wrong column
|
||||
flat_load_dword v1, v[3:4] offset:4095
|
||||
// GFX9: flat_load_dword v1, v[3:4] offset:4095 ; encoding: [0xff,0x0f,0x50,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:4096
|
||||
// GCNERR: :28: error: invalid operand for instruction
|
||||
// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
|
||||
// GFX9-ERR: :28: error: expected a 12-bit unsigned offset
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:4 glc
|
||||
// GFX9: flat_load_dword v1, v[3:4] offset:4 glc ; encoding: [0x04,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_load_dword v1, v[3:4] offset:4 glc slc
|
||||
// GFX9: flat_load_dword v1, v[3:4] offset:4 glc slc ; encoding: [0x04,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_atomic_add v[3:4], v5 offset:8 slc
|
||||
// GFX9: flat_atomic_add v[3:4], v5 offset:8 slc ; encoding: [0x08,0x00,0x0a,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_atomic_add v[3:4], v5 inst_offset:8 slc
|
||||
// GFX9: flat_atomic_add v[3:4], v5 offset:8 slc ; encoding: [0x08,0x00,0x0a,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_atomic_cmpswap v[1:2], v[3:4] offset:4095
|
||||
// GFX9: flat_atomic_cmpswap v[1:2], v[3:4] offset:4095 ; encoding: [0xff,0x0f,0x04,0xdd,0x01,0x03,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :36: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_atomic_cmpswap v[1:2], v[3:4] offset:4095 slc
|
||||
// GFX9: flat_atomic_cmpswap v[1:2], v[3:4] offset:4095 slc ; encoding: [0xff,0x0f,0x06,0xdd,0x01,0x03,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :36: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_atomic_cmpswap v[1:2], v[3:4]
|
||||
// GFX9: flat_atomic_cmpswap v[1:2], v[3:4] ; encoding: [0x00,0x00,0x04,0xdd,0x01,0x03,0x00,0x00]
|
||||
|
|
@ -59,11 +61,11 @@ flat_atomic_cmpswap v[1:2], v[3:4] glc
|
|||
|
||||
flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
|
||||
// GFX9: flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc ; encoding: [0xff,0x0f,0x05,0xdd,0x01,0x03,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :40: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc slc
|
||||
// GFX9: flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc slc ; encoding: [0xff,0x0f,0x07,0xdd,0x01,0x03,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :40: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_atomic_cmpswap v0, v[1:2], v[3:4] glc
|
||||
// GFX9: flat_atomic_cmpswap v0, v[1:2], v[3:4] glc ; encoding: [0x00,0x00,0x05,0xdd,0x01,0x03,0x00,0x00]
|
||||
|
|
@ -85,11 +87,11 @@ flat_atomic_cmpswap v0, v[1:2], v[3:4] slc
|
|||
|
||||
flat_atomic_swap v[3:4], v5 offset:16
|
||||
// GFX9: flat_atomic_swap v[3:4], v5 offset:16 ; encoding: [0x10,0x00,0x00,0xdd,0x03,0x05,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :29: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_store_dword v[3:4], v1 offset:16
|
||||
// GFX9: flat_store_dword v[3:4], v1 offset:16 ; encoding: [0x10,0x00,0x70,0xdc,0x03,0x01,0x00,0x00]
|
||||
// VIERR: :1: error: invalid operand for instruction
|
||||
// VI-ERR: :29: error: flat offset modifier is not supported on this GPU
|
||||
|
||||
flat_store_dword v[3:4], v1, off
|
||||
// GCNERR: :30: error: invalid operand for instruction
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ global_load_dword v1, v[3:4], off offset:0
|
|||
// VI-ERR: :35: error: not a valid operand.
|
||||
|
||||
global_load_dword v1, v[3:4], off offset:4095
|
||||
// GFX10-ERR: error: invalid operand for instruction
|
||||
// GFX10-ERR: :35: error: expected a 12-bit signed offset
|
||||
// GFX9: global_load_dword v1, v[3:4], off offset:4095 ; encoding: [0xff,0x8f,0x50,0xdc,0x03,0x00,0x7f,0x01]
|
||||
// VI-ERR: :35: error: not a valid operand.
|
||||
|
||||
|
|
@ -102,18 +102,18 @@ global_load_dword v1, v[3:4], off offset:-1
|
|||
// VI-ERR: :35: error: not a valid operand.
|
||||
|
||||
global_load_dword v1, v[3:4], off offset:-4096
|
||||
// GFX10-ERR: error: invalid operand for instruction
|
||||
// GFX10-ERR: :35: error: expected a 12-bit signed offset
|
||||
// GFX9: global_load_dword v1, v[3:4], off offset:-4096 ; encoding: [0x00,0x90,0x50,0xdc,0x03,0x00,0x7f,0x01]
|
||||
// VI-ERR: :35: error: not a valid operand.
|
||||
|
||||
global_load_dword v1, v[3:4], off offset:4096
|
||||
// GFX10-ERR: error: invalid operand for instruction
|
||||
// GFX9-ERR: :35: error: invalid operand for instruction
|
||||
// GFX10-ERR: :35: error: expected a 12-bit signed offset
|
||||
// GFX9-ERR: :35: error: expected a 13-bit signed offset
|
||||
// VI-ERR: :35: error: not a valid operand.
|
||||
|
||||
global_load_dword v1, v[3:4] off, offset:-4097
|
||||
// GFX10-ERR: error: invalid operand for instruction
|
||||
// GFX9-ERR: :35: error: invalid operand for instruction
|
||||
// GFX10-ERR: :35: error: expected a 12-bit signed offset
|
||||
// GFX9-ERR: :35: error: expected a 13-bit signed offset
|
||||
// VI-ERR: :35: error: not a valid operand.
|
||||
|
||||
global_store_byte v[3:4], v1, off
|
||||
|
|
|
|||
|
|
@ -91,9 +91,9 @@ scratch_load_dword v1, v2, off offset:0
|
|||
// VI-ERR: error: not a valid operand.
|
||||
|
||||
scratch_load_dword v1, v2, off offset:4095
|
||||
// GFX10-ERR: error: invalid operand for instruction
|
||||
// GFX10-ERR: :32: error: expected a 12-bit signed offset
|
||||
// GFX9: scratch_load_dword v1, v2, off offset:4095 ; encoding: [0xff,0x4f,0x50,0xdc,0x02,0x00,0x7f,0x01]
|
||||
// VI-ERR: error: not a valid operand.
|
||||
// VI-ERR: :32: error: not a valid operand.
|
||||
|
||||
scratch_load_dword v1, v2, off offset:-1
|
||||
// GFX10: encoding: [0xff,0x4f,0x30,0xdc,0x02,0x00,0x7d,0x01]
|
||||
|
|
@ -101,19 +101,19 @@ scratch_load_dword v1, v2, off offset:-1
|
|||
// VI-ERR: error: not a valid operand.
|
||||
|
||||
scratch_load_dword v1, v2, off offset:-4096
|
||||
// GFX10-ERR: error: invalid operand for instruction
|
||||
// GFX10-ERR: :32: error: expected a 12-bit signed offset
|
||||
// GFX9: scratch_load_dword v1, v2, off offset:-4096 ; encoding: [0x00,0x50,0x50,0xdc,0x02,0x00,0x7f,0x01]
|
||||
// VI-ERR: error: not a valid operand.
|
||||
// VI-ERR: :32: error: not a valid operand.
|
||||
|
||||
scratch_load_dword v1, v2, off offset:4096
|
||||
// GFX10-ERR: error: invalid operand for instruction
|
||||
// GFX9-ERR: error: invalid operand for instruction
|
||||
// VI-ERR: error: not a valid operand.
|
||||
// GFX10-ERR: :32: error: expected a 12-bit signed offset
|
||||
// GFX9-ERR: :32: error: expected a 13-bit signed offset
|
||||
// VI-ERR: :32: error: not a valid operand.
|
||||
|
||||
scratch_load_dword v1, v2, off offset:-4097
|
||||
// GFX10-ERR: error: invalid operand for instruction
|
||||
// GFX9-ERR: error: invalid operand for instruction
|
||||
// VI-ERR: error: not a valid operand.
|
||||
// GFX10-ERR: :32: error: expected a 12-bit signed offset
|
||||
// GFX9-ERR: :32: error: expected a 13-bit signed offset
|
||||
// VI-ERR: :32: error: not a valid operand.
|
||||
|
||||
scratch_store_byte v1, v2, off
|
||||
// GFX10: encoding: [0x00,0x40,0x60,0xdc,0x01,0x02,0x7d,0x00]
|
||||
|
|
|
|||
Loading…
Reference in New Issue