forked from OSchip/llvm-project
[PowerPC] Add vector conversion builtins to altivec.h - LLVM portion
This patch corresponds to review: https://reviews.llvm.org/D26307 Adds all the intrinsics used for various conversion builtins that will be added to altivec.h. These are type conversions between various types of vectors. llvm-svn: 286596
This commit is contained in:
Nemanja Ivanovic
parent
e47f2cd0c4
commit
2efc3cb968
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@ -806,6 +806,30 @@ def int_ppc_vsx_xviexpdp :
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def int_ppc_vsx_xviexpsp :
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PowerPC_VSX_Intrinsic<"xviexpsp",[llvm_v4f32_ty],
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[llvm_v4i32_ty, llvm_v4i32_ty],[IntrNoMem]>;
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def int_ppc_vsx_xvcvdpsxws :
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PowerPC_VSX_Intrinsic<"xvcvdpsxws", [llvm_v4i32_ty],
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[llvm_v2f64_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcvdpuxws :
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PowerPC_VSX_Intrinsic<"xvcvdpuxws", [llvm_v4i32_ty],
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[llvm_v2f64_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcvsxwdp :
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PowerPC_VSX_Intrinsic<"xvcvsxwdp", [llvm_v2f64_ty],
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[llvm_v4i32_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcvuxwdp :
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PowerPC_VSX_Intrinsic<"xvcvuxwdp", [llvm_v2f64_ty],
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[llvm_v4i32_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcvspdp :
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PowerPC_VSX_Intrinsic<"xvcvspdp", [llvm_v2f64_ty],
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[llvm_v4f32_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcvsxdsp :
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PowerPC_VSX_Intrinsic<"xvcvsxdsp", [llvm_v4f32_ty],
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[llvm_v2i64_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcvuxdsp :
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PowerPC_VSX_Intrinsic<"xvcvuxdsp", [llvm_v4f32_ty],
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[llvm_v2i64_ty], [IntrNoMem]>;
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def int_ppc_vsx_xvcvdpsp :
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PowerPC_VSX_Intrinsic<"xvcvdpsp", [llvm_v4f32_ty],
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[llvm_v2f64_ty], [IntrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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@ -596,25 +596,29 @@ let Uses = [RM] in {
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def XVCVDPSP : XX2Form<60, 393,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpsp $XT, $XB", IIC_VecFP, []>;
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"xvcvdpsp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (int_ppc_vsx_xvcvdpsp v2f64:$XB))]>;
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def XVCVDPSXDS : XX2Form<60, 472,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpsxds $XT, $XB", IIC_VecFP,
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[(set v2i64:$XT, (fp_to_sint v2f64:$XB))]>;
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def XVCVDPSXWS : XX2Form<60, 216,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpsxws $XT, $XB", IIC_VecFP, []>;
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"xvcvdpsxws $XT, $XB", IIC_VecFP,
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[(set v4i32:$XT, (int_ppc_vsx_xvcvdpsxws v2f64:$XB))]>;
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def XVCVDPUXDS : XX2Form<60, 456,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpuxds $XT, $XB", IIC_VecFP,
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[(set v2i64:$XT, (fp_to_uint v2f64:$XB))]>;
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def XVCVDPUXWS : XX2Form<60, 200,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvdpuxws $XT, $XB", IIC_VecFP, []>;
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"xvcvdpuxws $XT, $XB", IIC_VecFP,
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[(set v4i32:$XT, (int_ppc_vsx_xvcvdpuxws v2f64:$XB))]>;
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def XVCVSPDP : XX2Form<60, 457,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspdp $XT, $XB", IIC_VecFP, []>;
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"xvcvspdp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (int_ppc_vsx_xvcvspdp v4f32:$XB))]>;
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def XVCVSPSXDS : XX2Form<60, 408,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvspsxds $XT, $XB", IIC_VecFP, []>;
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@ -633,10 +637,12 @@ let Uses = [RM] in {
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[(set v2f64:$XT, (sint_to_fp v2i64:$XB))]>;
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def XVCVSXDSP : XX2Form<60, 440,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxdsp $XT, $XB", IIC_VecFP, []>;
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"xvcvsxdsp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (int_ppc_vsx_xvcvsxdsp v2i64:$XB))]>;
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def XVCVSXWDP : XX2Form<60, 248,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxwdp $XT, $XB", IIC_VecFP, []>;
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"xvcvsxwdp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (int_ppc_vsx_xvcvsxwdp v4i32:$XB))]>;
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def XVCVSXWSP : XX2Form<60, 184,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvsxwsp $XT, $XB", IIC_VecFP,
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@ -647,10 +653,12 @@ let Uses = [RM] in {
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[(set v2f64:$XT, (uint_to_fp v2i64:$XB))]>;
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def XVCVUXDSP : XX2Form<60, 424,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxdsp $XT, $XB", IIC_VecFP, []>;
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"xvcvuxdsp $XT, $XB", IIC_VecFP,
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[(set v4f32:$XT, (int_ppc_vsx_xvcvuxdsp v2i64:$XB))]>;
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def XVCVUXWDP : XX2Form<60, 232,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxwdp $XT, $XB", IIC_VecFP, []>;
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"xvcvuxwdp $XT, $XB", IIC_VecFP,
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[(set v2f64:$XT, (int_ppc_vsx_xvcvuxwdp v4i32:$XB))]>;
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def XVCVUXWSP : XX2Form<60, 168,
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(outs vsrc:$XT), (ins vsrc:$XB),
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"xvcvuxwsp $XT, $XB", IIC_VecFP, []>;
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@ -158,6 +158,80 @@ entry:
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; CHECK: xvredp {{[0-9]+}}, {{[0-9]+}}
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}
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; Function Attrs: nounwind readnone
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define <4 x i32> @emit_xvcvdpsxws(<2 x double> %a) {
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double> %a)
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ret <4 x i32> %0
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; CHECK-LABEL: @emit_xvcvdpsxws
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; CHECK: xvcvdpsxws 34, 34
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}
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; Function Attrs: nounwind readnone
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define <4 x i32> @emit_xvcvdpuxws(<2 x double> %a) {
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entry:
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%0 = tail call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double> %a)
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ret <4 x i32> %0
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; CHECK-LABEL: @emit_xvcvdpuxws
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; CHECK: xvcvdpuxws 34, 34
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}
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; Function Attrs: nounwind readnone
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define <2 x double> @emit_xvcvsxwdp(<4 x i32> %a) {
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entry:
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%0 = tail call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> %a)
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ret <2 x double> %0
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; CHECK-LABEL: @emit_xvcvsxwdp
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; CHECK: xvcvsxwdp 34, 34
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}
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; Function Attrs: nounwind readnone
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define <2 x double> @emit_xvcvuxwdp(<4 x i32> %a) {
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entry:
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%0 = tail call <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32> %a)
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ret <2 x double> %0
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; CHECK-LABEL: @emit_xvcvuxwdp
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; CHECK: xvcvuxwdp 34, 34
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}
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; Function Attrs: nounwind readnone
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define <2 x double> @emit_xvcvspdp(<4 x float> %a) {
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entry:
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%0 = tail call <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float> %a)
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ret <2 x double> %0
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; CHECK-LABEL: @emit_xvcvspdp
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; CHECK: xvcvspdp 34, 34
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}
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; Function Attrs: nounwind readnone
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define <4 x float> @emit_xvcvsxdsp(<2 x i64> %a) {
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entry:
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%0 = tail call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> %a)
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ret <4 x float> %0
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; CHECK-LABEL: @emit_xvcvsxdsp
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; CHECK: xvcvsxdsp 34, 34
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}
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; Function Attrs: nounwind readnone
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define <4 x float> @emit_xvcvuxdsp(<2 x i64> %a) {
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entry:
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%0 = tail call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> %a)
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ret <4 x float> %0
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; CHECK-LABEL: @emit_xvcvuxdsp
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; CHECK: xvcvuxdsp 34, 34
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}
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; Function Attrs: nounwind readnone
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define <4 x float> @emit_xvcvdpsp(<2 x double> %a) {
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entry:
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%0 = tail call <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double> %a)
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ret <4 x float> %0
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; CHECK-LABEL: @emit_xvcvdpsp
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; CHECK: xvcvdpsp 34, 34
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}
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; Function Attrs: nounwind readnone
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.ppc.vsx.xvresp(<4 x float>)
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@ -193,3 +267,11 @@ declare <2 x i64> @llvm.ppc.vsx.xvcmpgtdp(<2 x double>, <2 x double>)
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; Function Attrs: nounwind readnone
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declare <4 x i32> @llvm.ppc.vsx.xvcmpgtsp(<4 x float>, <4 x float>)
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declare <4 x float> @llvm.ppc.vsx.xvcvdpsp(<2 x double>) #1
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declare <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>) #1
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declare <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>) #1
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declare <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>) #1
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declare <2 x double> @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>) #1
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declare <2 x double> @llvm.ppc.vsx.xvcvspdp(<4 x float>) #1
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declare <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64>) #1
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declare <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64>) #1
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