forked from OSchip/llvm-project
Implement X86TTI::getUnrollingPreferences
This provides an initial implementation of getUnrollingPreferences for x86. getUnrollingPreferences is used by the generic (concatenation) unroller, which is distinct from the unrolling done by the loop vectorizer. Many modern x86 cores have some kind of uop cache and loop-stream detector (LSD) used to efficiently dispatch small loops, and taking full advantage of this requires unrolling small loops (small here means 10s of uops). These caches also have limits on the number of taken branches in the loop, and so we also cap the loop unrolling factor based on the maximum "depth" of the loop. This is currently calculated with a partial DFS traversal (partial because it will stop early if the path length grows too much). This is still an approximation, and one that is both conservative (because it does not account for branches eliminated via block placement) and optimistic (because it is only recording the maximum depth over minimum paths). Nevertheless, because the loops that fit in these uop caches are so small, it is not clear how much the details matter. The original set of patches posted for review produced the following test-suite performance results (from the TSVC benchmark) at that time: ControlLoops-dbl - 13% speedup ControlLoops-flt - 15% speedup Reductions-dbl - 7.5% speedup llvm-svn: 205348
This commit is contained in:
Hal Finkel
parent
6386cb8d4d
commit
2eed29f3c8
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@ -17,8 +17,11 @@
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#define DEBUG_TYPE "x86tti"
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#include "X86.h"
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#include "X86TargetMachine.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/Analysis/LoopInfo.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/CostTable.h"
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#include "llvm/Target/TargetLowering.h"
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@ -31,6 +34,17 @@ namespace llvm {
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void initializeX86TTIPass(PassRegistry &);
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}
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static cl::opt<bool>
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UsePartialUnrolling("x86-use-partial-unrolling", cl::init(true),
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cl::desc("Use partial unrolling for some X86 targets"), cl::Hidden);
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static cl::opt<unsigned>
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PartialUnrollingThreshold("x86-partial-unrolling-threshold", cl::init(0),
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cl::desc("Threshold for X86 partial unrolling"), cl::Hidden);
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static cl::opt<unsigned>
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PartialUnrollingMaxBranches("x86-partial-max-branches", cl::init(2),
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cl::desc("Threshold for taken branches in X86 partial unrolling"),
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cl::Hidden);
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namespace {
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class X86TTI final : public ImmutablePass, public TargetTransformInfo {
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@ -73,6 +87,8 @@ public:
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/// \name Scalar TTI Implementations
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/// @{
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PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override;
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void getUnrollingPreferences(Loop *L,
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UnrollingPreferences &UP) const override;
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/// @}
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@ -137,6 +153,93 @@ X86TTI::PopcntSupportKind X86TTI::getPopcntSupport(unsigned TyWidth) const {
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return ST->hasPOPCNT() ? PSK_FastHardware : PSK_Software;
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}
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void X86TTI::getUnrollingPreferences(Loop *L, UnrollingPreferences &UP) const {
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if (!UsePartialUnrolling)
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return;
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// According to the Intel 64 and IA-32 Architectures Optimization Reference
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// Manual, Intel Core models and later have a loop stream detector
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// (and associated uop queue) that can benefit from partial unrolling.
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// The relevant requirements are:
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// - The loop must have no more than 4 (8 for Nehalem and later) branches
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// taken, and none of them may be calls.
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// - The loop can have no more than 18 (28 for Nehalem and later) uops.
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// According to the Software Optimization Guide for AMD Family 15h Processors,
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// models 30h-4fh (Steamroller and later) have a loop predictor and loop
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// buffer which can benefit from partial unrolling.
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// The relevant requirements are:
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// - The loop must have fewer than 16 branches
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// - The loop must have less than 40 uops in all executed loop branches
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unsigned MaxBranches, MaxOps;
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if (PartialUnrollingThreshold.getNumOccurrences() > 0) {
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MaxBranches = PartialUnrollingMaxBranches;
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MaxOps = PartialUnrollingThreshold;
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} else if (ST->isAtom()) {
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// On the Atom, the throughput for taken branches is 2 cycles. For small
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// simple loops, expand by a small factor to hide the backedge cost.
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MaxBranches = 2;
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MaxOps = 10;
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} else if (ST->hasFSGSBase() && ST->hasXOP() /* Steamroller and later */) {
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MaxBranches = 16;
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MaxOps = 40;
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} else if (ST->hasFMA4() /* Any other recent AMD */) {
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return;
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} else if (ST->hasAVX() || ST->hasSSE42() /* Nehalem and later */) {
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MaxBranches = 8;
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MaxOps = 28;
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} else if (ST->hasSSSE3() /* Intel Core */) {
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MaxBranches = 4;
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MaxOps = 18;
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} else {
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return;
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}
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// Scan the loop: don't unroll loops with calls, and count the potential
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// number of taken branches (this is somewhat conservative because we're
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// counting all block transitions as potential branches while in reality some
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// of these will become implicit via block placement).
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unsigned MaxDepth = 0;
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for (df_iterator<BasicBlock*> DI = df_begin(L->getHeader()),
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DE = df_end(L->getHeader()); DI != DE;) {
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if (!L->contains(*DI)) {
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DI.skipChildren();
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continue;
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}
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MaxDepth = std::max(MaxDepth, DI.getPathLength());
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if (MaxDepth > MaxBranches)
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return;
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for (BasicBlock::iterator I = DI->begin(), IE = DI->end(); I != IE; ++I)
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if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
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ImmutableCallSite CS(I);
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if (const Function *F = CS.getCalledFunction()) {
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if (!isLoweredToCall(F))
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continue;
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}
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return;
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}
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++DI;
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}
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// Enable runtime and partial unrolling up to the specified size.
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UP.Partial = UP.Runtime = true;
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UP.PartialThreshold = UP.PartialOptSizeThreshold = MaxOps;
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// Set the maximum count based on the loop depth. The maximum number of
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// branches taken in a loop (including the backedge) is equal to the maximum
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// loop depth (the DFS path length from the loop header to any block in the
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// loop). When the loop is unrolled, this depth (except for the backedge
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// itself) is multiplied by the unrolling factor. This new unrolled depth
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// must be less than the target-specific maximum branch count (which limits
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// the number of taken branches in the uop buffer).
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if (MaxDepth > 1)
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UP.MaxCount = (MaxBranches-1)/(MaxDepth-1);
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}
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unsigned X86TTI::getNumberOfRegisters(bool Vector) const {
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if (Vector && !ST->hasSSE1())
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return 0;
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@ -0,0 +1,4 @@
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targets = set(config.root.targets_to_build.split())
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if not 'X86' in targets:
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config.unsupported = True
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@ -0,0 +1,80 @@
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; RUN: opt < %s -S -loop-unroll -mcpu=nehalem -x86-use-partial-unrolling=1 | FileCheck %s
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; RUN: opt < %s -S -loop-unroll -mcpu=core -x86-use-partial-unrolling=1 | FileCheck -check-prefix=CHECK-NOUNRL %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @foo(i32* noalias nocapture readnone %ip, double %alpha, double* noalias nocapture %a, double* noalias nocapture readonly %b) #0 {
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entry:
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br label %vector.body
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vector.body: ; preds = %vector.body, %entry
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%0 = getelementptr inbounds double* %b, i64 %index
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%1 = bitcast double* %0 to <2 x double>*
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%wide.load = load <2 x double>* %1, align 8
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%.sum9 = or i64 %index, 2
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%2 = getelementptr double* %b, i64 %.sum9
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%3 = bitcast double* %2 to <2 x double>*
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%wide.load8 = load <2 x double>* %3, align 8
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%4 = fadd <2 x double> %wide.load, <double 1.000000e+00, double 1.000000e+00>
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%5 = fadd <2 x double> %wide.load8, <double 1.000000e+00, double 1.000000e+00>
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%6 = getelementptr inbounds double* %a, i64 %index
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%7 = bitcast double* %6 to <2 x double>*
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store <2 x double> %4, <2 x double>* %7, align 8
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%.sum10 = or i64 %index, 2
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%8 = getelementptr double* %a, i64 %.sum10
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%9 = bitcast double* %8 to <2 x double>*
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store <2 x double> %5, <2 x double>* %9, align 8
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%index.next = add i64 %index, 4
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%10 = icmp eq i64 %index.next, 1600
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br i1 %10, label %for.end, label %vector.body
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; FIXME: We should probably unroll this loop by a factor of 2, but the cost
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; model needs to be fixed to account for instructions likely to be folded
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; as part of an addressing mode.
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; CHECK-LABEL: @foo
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; CHECK-NOUNRL-LABEL: @foo
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for.end: ; preds = %vector.body
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ret void
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}
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define void @bar(i32* noalias nocapture readnone %ip, double %alpha, double* noalias nocapture %a, double* noalias nocapture readonly %b) #0 {
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entry:
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br label %vector.body
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vector.body: ; preds = %vector.body, %entry
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%v0 = getelementptr inbounds double* %b, i64 %index
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%v1 = bitcast double* %v0 to <2 x double>*
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%wide.load = load <2 x double>* %v1, align 8
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%v4 = fadd <2 x double> %wide.load, <double 1.000000e+00, double 1.000000e+00>
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%v5 = fmul <2 x double> %v4, <double 8.000000e+00, double 8.000000e+00>
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%v6 = getelementptr inbounds double* %a, i64 %index
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%v7 = bitcast double* %v6 to <2 x double>*
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store <2 x double> %v5, <2 x double>* %v7, align 8
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%index.next = add i64 %index, 2
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%v10 = icmp eq i64 %index.next, 1600
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br i1 %v10, label %for.end, label %vector.body
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; FIXME: We should probably unroll this loop by a factor of 2, but the cost
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; model needs to first to fixed to account for instructions likely to be folded
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; as part of an addressing mode.
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; CHECK-LABEL: @bar
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; CHECK: fadd
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; CHECK-NEXT: fmul
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; CHECK: fadd
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; CHECK-NEXT: fmul
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; CHECK-NOUNRL-LABEL: @bar
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; CHECK-NOUNRL: fadd
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; CHECK-NOUNRL-NEXT: fmul
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; CHECK-NOUNRL-NOT: fadd
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for.end: ; preds = %vector.body
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ret void
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}
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attributes #0 = { nounwind uwtable }
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@ -1,13 +1,13 @@
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; RUN: opt < %s -mcpu=corei7 -O1 -S | FileCheck %s --check-prefix=O1
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; RUN: opt < %s -mcpu=corei7 -O2 -S | FileCheck %s --check-prefix=O2
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; RUN: opt < %s -mcpu=corei7 -O3 -S | FileCheck %s --check-prefix=O3
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; RUN: opt < %s -mcpu=corei7 -Os -S | FileCheck %s --check-prefix=Os
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; RUN: opt < %s -mcpu=corei7 -Oz -S | FileCheck %s --check-prefix=Oz
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; RUN: opt < %s -mcpu=corei7 -O1 -vectorize-loops -S | FileCheck %s --check-prefix=O1VEC
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; RUN: opt < %s -mcpu=corei7 -Oz -vectorize-loops -S | FileCheck %s --check-prefix=OzVEC
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; RUN: opt < %s -mcpu=corei7 -O1 -loop-vectorize -S | FileCheck %s --check-prefix=O1VEC2
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; RUN: opt < %s -mcpu=corei7 -Oz -loop-vectorize -S | FileCheck %s --check-prefix=OzVEC2
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; RUN: opt < %s -mcpu=corei7 -O3 -disable-loop-vectorization -S | FileCheck %s --check-prefix=O3DIS
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; RUN: opt < %s -mcpu=corei7 -O1 -S -x86-use-partial-unrolling=0 | FileCheck %s --check-prefix=O1
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; RUN: opt < %s -mcpu=corei7 -O2 -S -x86-use-partial-unrolling=0 | FileCheck %s --check-prefix=O2
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; RUN: opt < %s -mcpu=corei7 -O3 -S -x86-use-partial-unrolling=0 | FileCheck %s --check-prefix=O3
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; RUN: opt < %s -mcpu=corei7 -Os -S -x86-use-partial-unrolling=0 | FileCheck %s --check-prefix=Os
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; RUN: opt < %s -mcpu=corei7 -Oz -S -x86-use-partial-unrolling=0 | FileCheck %s --check-prefix=Oz
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; RUN: opt < %s -mcpu=corei7 -O1 -vectorize-loops -S -x86-use-partial-unrolling=0 | FileCheck %s --check-prefix=O1VEC
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; RUN: opt < %s -mcpu=corei7 -Oz -vectorize-loops -S -x86-use-partial-unrolling=0 | FileCheck %s --check-prefix=OzVEC
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; RUN: opt < %s -mcpu=corei7 -O1 -loop-vectorize -S -x86-use-partial-unrolling=0 | FileCheck %s --check-prefix=O1VEC2
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; RUN: opt < %s -mcpu=corei7 -Oz -loop-vectorize -S -x86-use-partial-unrolling=0 | FileCheck %s --check-prefix=OzVEC2
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; RUN: opt < %s -mcpu=corei7 -O3 -disable-loop-vectorization -S -x86-use-partial-unrolling=0 | FileCheck %s --check-prefix=O3DIS
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; This file tests the llvm.vectorizer.pragma forcing vectorization even when
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; optimization levels are too low, or when vectorization is disabled.
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