diff --git a/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll b/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll
index 6fa4d70d6360..735b07c6b928 100644
--- a/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll
+++ b/llvm/test/Transforms/InstCombine/zext-bool-add-sub.ll
@@ -1,12 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 ; rdar://11748024
 
 define i32 @a(i1 zeroext %x, i1 zeroext %y) {
-entry:
 ; CHECK-LABEL: @a(
-; CHECK: [[TMP1:%.*]] = sext i1 %y to i32
-; CHECK: [[TMP2:%.*]] = select i1 %x, i32 2, i32 1
-; CHECK-NEXT: add nsw i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[CONV3_NEG:%.*]] = sext i1 %y to i32
+; CHECK-NEXT:    [[SUB:%.*]] = select i1 %x, i32 2, i32 1
+; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[SUB]], [[CONV3_NEG]]
+; CHECK-NEXT:    ret i32 [[ADD]]
+;
   %conv = zext i1 %x to i32
   %conv3 = zext i1 %y to i32
   %conv3.neg = sub i32 0, %conv3
@@ -14,3 +16,4 @@ entry:
   %add = add i32 %sub, %conv3.neg
   ret i32 %add
 }
+