forked from OSchip/llvm-project
Add empty patterns to all F3_1 instructions
llvm-svn: 24776
This commit is contained in:
Chris Lattner
parent
1d71248392
commit
2edb4b7f99
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@ -62,12 +62,14 @@ class F3 : InstV8 {
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// Specific F3 classes: SparcV8 manual, page 44
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//
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class F3_1<bits<2> opVal, bits<6> op3val, dag ops, string asmstr> : F3 {
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class F3_1<bits<2> opVal, bits<6> op3val, dag ops,
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string asmstr, list<dag> pattern> : F3 {
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bits<8> asi = 0; // asi not currently used in SparcV8
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bits<5> rs2;
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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let op = opVal;
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let op3 = op3val;
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@ -100,19 +100,19 @@ def LDD : F3_2<3, 0b000011,
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFrr : F3_1<3, 0b100000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ld [$b+$c], $dst">;
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"ld [$b+$c], $dst", []>;
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def LDFri : F3_2<3, 0b100000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst", []>;
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def LDDFrr : F3_1<3, 0b100011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ldd [$b+$c], $dst">;
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"ldd [$b+$c], $dst", []>;
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def LDDFri : F3_2<3, 0b100011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ldd [$b+$c], $dst", []>;
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def LDFSRrr: F3_1<3, 0b100001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"ld [$b+$c], $dst">;
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"ld [$b+$c], $dst", []>;
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def LDFSRri: F3_2<3, 0b100001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"ld [$b+$c], $dst", []>;
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@ -134,25 +134,25 @@ def STD : F3_2<3, 0b000111,
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"st $src, [$base+$offset]">;
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"st $src, [$base+$offset]", []>;
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def STFri : F3_2<3, 0b100100,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]", []>;
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def STDFrr : F3_1<3, 0b100111,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"std $src, [$base+$offset]">;
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"std $src, [$base+$offset]", []>;
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def STDFri : F3_2<3, 0b100111,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]", []>;
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def STFSRrr : F3_1<3, 0b100101,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"st $src, [$base+$offset]">;
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"st $src, [$base+$offset]", []>;
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def STFSRri : F3_2<3, 0b100101,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"st $src, [$base+$offset]", []>;
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def STDFQrr : F3_1<3, 0b100110,
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(ops IntRegs:$base, IntRegs:$offset, IntRegs:$src),
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"std $src, [$base+$offset]">;
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"std $src, [$base+$offset]", []>;
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def STDFQri : F3_2<3, 0b100110,
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(ops IntRegs:$base, IntRegs:$offset, i32imm:$src),
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"std $src, [$base+$offset]", []>;
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@ -170,76 +170,76 @@ let rd = 0, imm22 = 0 in
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// Section B.11 - Logical Instructions, p. 106
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def ANDrr : F3_1<2, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"and $b, $c, $dst">;
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"and $b, $c, $dst", []>;
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def ANDri : F3_2<2, 0b000001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"and $b, $c, $dst",
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[(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
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def ANDCCrr : F3_1<2, 0b010001,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andcc $b, $c, $dst">;
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"andcc $b, $c, $dst", []>;
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def ANDCCri : F3_2<2, 0b010001,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andcc $b, $c, $dst", []>;
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def ANDNrr : F3_1<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andn $b, $c, $dst">;
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"andn $b, $c, $dst", []>;
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def ANDNri : F3_2<2, 0b000101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andn $b, $c, $dst", []>;
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def ANDNCCrr: F3_1<2, 0b010101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"andncc $b, $c, $dst">;
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"andncc $b, $c, $dst", []>;
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def ANDNCCri: F3_2<2, 0b010101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"andncc $b, $c, $dst", []>;
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def ORrr : F3_1<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"or $b, $c, $dst">;
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"or $b, $c, $dst", []>;
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def ORri : F3_2<2, 0b000010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"or $b, $c, $dst",
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[(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
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def ORCCrr : F3_1<2, 0b010010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orcc $b, $c, $dst">;
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"orcc $b, $c, $dst", []>;
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def ORCCri : F3_2<2, 0b010010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orcc $b, $c, $dst", []>;
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def ORNrr : F3_1<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orn $b, $c, $dst">;
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"orn $b, $c, $dst", []>;
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def ORNri : F3_2<2, 0b000110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orn $b, $c, $dst", []>;
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def ORNCCrr : F3_1<2, 0b010110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"orncc $b, $c, $dst">;
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"orncc $b, $c, $dst", []>;
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def ORNCCri : F3_2<2, 0b010110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"orncc $b, $c, $dst", []>;
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def XORrr : F3_1<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xor $b, $c, $dst">;
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"xor $b, $c, $dst", []>;
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def XORri : F3_2<2, 0b000011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xor $b, $c, $dst",
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[(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
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def XORCCrr : F3_1<2, 0b010011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xorcc $b, $c, $dst">;
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"xorcc $b, $c, $dst", []>;
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def XORCCri : F3_2<2, 0b010011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xorcc $b, $c, $dst", []>;
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def XNORrr : F3_1<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xnor $b, $c, $dst">;
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"xnor $b, $c, $dst", []>;
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def XNORri : F3_2<2, 0b000111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xnor $b, $c, $dst", []>;
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def XNORCCrr: F3_1<2, 0b010111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"xnorcc $b, $c, $dst">;
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"xnorcc $b, $c, $dst", []>;
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def XNORCCri: F3_2<2, 0b010111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"xnorcc $b, $c, $dst", []>;
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@ -247,19 +247,19 @@ def XNORCCri: F3_2<2, 0b010111,
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sll $b, $c, $dst">;
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"sll $b, $c, $dst", []>;
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def SLLri : F3_2<2, 0b100101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sll $b, $c, $dst", []>;
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def SRLrr : F3_1<2, 0b100110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"srl $b, $c, $dst">;
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"srl $b, $c, $dst", []>;
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def SRLri : F3_2<2, 0b100110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"srl $b, $c, $dst", []>;
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def SRArr : F3_1<2, 0b100111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sra $b, $c, $dst">;
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"sra $b, $c, $dst", []>;
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def SRAri : F3_2<2, 0b100111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sla $b, $c, $dst", []>;
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@ -267,26 +267,26 @@ def SRAri : F3_2<2, 0b100111,
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// Section B.13 - Add Instructions, p. 108
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def ADDrr : F3_1<2, 0b000000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"add $b, $c, $dst">;
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"add $b, $c, $dst", []>;
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def ADDri : F3_2<2, 0b000000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"add $b, $c, $dst",
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[(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
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def ADDCCrr : F3_1<2, 0b010000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addcc $b, $c, $dst">;
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"addcc $b, $c, $dst", []>;
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def ADDCCri : F3_2<2, 0b010000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addcc $b, $c, $dst", []>;
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def ADDXrr : F3_1<2, 0b001000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addx $b, $c, $dst">;
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"addx $b, $c, $dst", []>;
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def ADDXri : F3_2<2, 0b001000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addx $b, $c, $dst", []>;
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def ADDXCCrr: F3_1<2, 0b011000,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"addxcc $b, $c, $dst">;
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"addxcc $b, $c, $dst", []>;
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def ADDXCCri: F3_2<2, 0b011000,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"addxcc $b, $c, $dst", []>;
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@ -294,26 +294,26 @@ def ADDXCCri: F3_2<2, 0b011000,
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// Section B.15 - Subtract Instructions, p. 110
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def SUBrr : F3_1<2, 0b000100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sub $b, $c, $dst">;
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"sub $b, $c, $dst", []>;
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def SUBri : F3_2<2, 0b000100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sub $b, $c, $dst",
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[(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
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def SUBCCrr : F3_1<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subcc $b, $c, $dst">;
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"subcc $b, $c, $dst", []>;
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def SUBCCri : F3_2<2, 0b010100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subcc $b, $c, $dst", []>;
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def SUBXrr : F3_1<2, 0b001100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subx $b, $c, $dst">;
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"subx $b, $c, $dst", []>;
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def SUBXri : F3_2<2, 0b001100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subx $b, $c, $dst", []>;
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def SUBXCCrr: F3_1<2, 0b011100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"subxcc $b, $c, $dst">;
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"subxcc $b, $c, $dst", []>;
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def SUBXCCri: F3_2<2, 0b011100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"subxcc $b, $c, $dst", []>;
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@ -321,25 +321,25 @@ def SUBXCCri: F3_2<2, 0b011100,
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// Section B.18 - Multiply Instructions, p. 113
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def UMULrr : F3_1<2, 0b001010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"umul $b, $c, $dst">;
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"umul $b, $c, $dst", []>;
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def UMULri : F3_2<2, 0b001010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"umul $b, $c, $dst", []>;
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def SMULrr : F3_1<2, 0b001011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"smul $b, $c, $dst">;
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"smul $b, $c, $dst", []>;
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def SMULri : F3_2<2, 0b001011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"smul $b, $c, $dst", []>;
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def UMULCCrr: F3_1<2, 0b011010,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"umulcc $b, $c, $dst">;
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"umulcc $b, $c, $dst", []>;
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def UMULCCri: F3_2<2, 0b011010,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"umulcc $b, $c, $dst", []>;
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def SMULCCrr: F3_1<2, 0b011011,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"smulcc $b, $c, $dst">;
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"smulcc $b, $c, $dst", []>;
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def SMULCCri: F3_2<2, 0b011011,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"smulcc $b, $c, $dst", []>;
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@ -347,25 +347,25 @@ def SMULCCri: F3_2<2, 0b011011,
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// Section B.19 - Divide Instructions, p. 115
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def UDIVrr : F3_1<2, 0b001110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"udiv $b, $c, $dst">;
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"udiv $b, $c, $dst", []>;
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def UDIVri : F3_2<2, 0b001110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"udiv $b, $c, $dst", []>;
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def SDIVrr : F3_1<2, 0b001111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sdiv $b, $c, $dst">;
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"sdiv $b, $c, $dst", []>;
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def SDIVri : F3_2<2, 0b001111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sdiv $b, $c, $dst", []>;
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def UDIVCCrr : F3_1<2, 0b011110,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"udivcc $b, $c, $dst">;
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"udivcc $b, $c, $dst", []>;
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def UDIVCCri : F3_2<2, 0b011110,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"udivcc $b, $c, $dst", []>;
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def SDIVCCrr : F3_1<2, 0b011111,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"sdivcc $b, $c, $dst">;
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"sdivcc $b, $c, $dst", []>;
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def SDIVCCri : F3_2<2, 0b011111,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"sdivcc $b, $c, $dst", []>;
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@ -373,13 +373,13 @@ def SDIVCCri : F3_2<2, 0b011111,
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// Section B.20 - SAVE and RESTORE, p. 117
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def SAVErr : F3_1<2, 0b111100,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"save $b, $c, $dst">;
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"save $b, $c, $dst", []>;
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def SAVEri : F3_2<2, 0b111100,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
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"save $b, $c, $dst", []>;
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def RESTORErr : F3_1<2, 0b111101,
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(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
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"restore $b, $c, $dst">;
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"restore $b, $c, $dst", []>;
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def RESTOREri : F3_2<2, 0b111101,
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(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"restore $b, $c, $dst", []>;
|
||||
|
|
@ -457,13 +457,13 @@ let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
|
|||
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
|
||||
def JMPLrr : F3_1<2, 0b111000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"jmpl $b+$c, $dst">;
|
||||
"jmpl $b+$c, $dst", []>;
|
||||
}
|
||||
|
||||
// Section B.29 - Write State Register Instructions
|
||||
def WRrr : F3_1<2, 0b110000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
|
||||
"wr $b, $c, $dst">;
|
||||
"wr $b, $c, $dst", []>;
|
||||
def WRri : F3_2<2, 0b110000,
|
||||
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
|
||||
"wr $b, $c, $dst", []>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue