forked from OSchip/llvm-project
[GlobalISel] More detailed skeleton for the IRTranslator.
llvm-svn: 260456
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@ -20,6 +20,7 @@
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#define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
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#define LLVM_CODEGEN_GLOBALISEL_IRTRANSLATOR_H
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#include "Types.h"
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#include "Types.h"
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#include "llvm/ADT/SetVector.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Constants.h"
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@ -52,17 +53,15 @@ private:
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// registers, but we would need to encapsulate that in a higher
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// registers, but we would need to encapsulate that in a higher
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// level class.
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// level class.
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ValueToVRegs ValToVRegs;
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ValueToVRegs ValToVRegs;
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// Mapping of a constant to the instructions to produce
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// that constant.
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// Constants are special because when we encounter one,
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// Constants are special because when we encounter one,
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// we do not know at first where to insert the definition since
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// we do not know at first where to insert the definition since
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// this depends on all its uses.
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// this depends on all its uses.
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// Thus, we will insert the sequences to materialize them when
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// Thus, we will insert the sequences to materialize them when
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// we know all their users.
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// we know all their users.
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// In the meantime, just keep it in a map.
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// In the meantime, just keep it in a set.
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// Note: Constants that end up as immediate in the related instructions,
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// Note: Constants that end up as immediate in the related instructions,
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// do not appear in that map.
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// do not appear in that map.
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DenseMap<const Constant *, SmallVector<MachineInstr *, 1>> ConstantToSequence;
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SmallSetVector<const Constant *, 8> Constants;
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/* A bunch of methods targeting ADD, SUB, etc. */
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/* A bunch of methods targeting ADD, SUB, etc. */
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// Return true if the translation was successful, false
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// Return true if the translation was successful, false
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@ -76,8 +75,14 @@ private:
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// 2 Update the ValToVReg accordingly.
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// 2 Update the ValToVReg accordingly.
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// 2.alt. For constant arguments, if they are compile time constants,
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// 2.alt. For constant arguments, if they are compile time constants,
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// produce an immediate in the right operand and do not touch
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// produce an immediate in the right operand and do not touch
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// ValToReg. Otherwise, update ValToVReg and register the
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// ValToReg. Actually we will go with a virtual register for each
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// sequence to materialize the constant in ConstantToSequence.
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// constants because it may be expensive to actually materialize the
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// constant. Moreover, if the constant spans on several instructions,
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// CSE may not catch them.
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// => Update ValToVReg and remember that we saw a constant in Constants.
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// We will materialize all the constants in finalize.
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// Note: we would need to do something so that we can recognize such operand
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// as constants.
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// 3. Create the generic instruction.
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// 3. Create the generic instruction.
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bool translateADD(const Instruction &Inst);
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bool translateADD(const Instruction &Inst);
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@ -94,20 +99,13 @@ private:
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// * Insert all the code needed to materialize the constants
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// * Insert all the code needed to materialize the constants
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// at the proper place. E.g., Entry block or dominator block
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// at the proper place. E.g., Entry block or dominator block
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// of each constant depending ob how fancy we want to be.
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// of each constant depending on how fancy we want to be.
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// * Clear the different maps.
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// * Clear the different maps.
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void finalize();
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void finalize();
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public:
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public:
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// Ctor, nothing fancy.
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// Ctor, nothing fancy.
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IRTranslator();
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IRTranslator();
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// Instead of having the instance of the IRTranslatorToolkit
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// as an argument of the constructor of IRTranslator, we ask
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// the target the instance of the toolkit for each MachineFunction.
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// The interest is that we may have different translator for different
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// subtract or optimization. E.g., we could have a translator optimized
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// to produce small code size.
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//
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// Algo:
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// Algo:
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// CallLowering = MF.subtarget.getCallLowering()
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// CallLowering = MF.subtarget.getCallLowering()
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// F = MF.getParent()
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// F = MF.getParent()
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@ -12,20 +12,39 @@
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/IR/Function.h"
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#define DEBUG_TYPE "irtranslator"
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using namespace llvm;
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using namespace llvm;
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char IRTranslator::ID = 0;
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char IRTranslator::ID = 0;
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bool IRTranslator::translateADD(const Instruction &Inst) {
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bool IRTranslator::translateADD(const Instruction &Inst) {
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// Get or create a virtual register for each value.
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// Unless the value is a Constant => loadimm cst?
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// or inline constant each time?
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// Creation of a virtual register needs to have a size.
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return false;
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return false;
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}
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}
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bool IRTranslator::translate(const Instruction &) {
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bool IRTranslator::translate(const Instruction &Inst) {
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return false;
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switch(Inst.getOpcode()) {
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case Instruction::Add: {
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return translateADD(Inst);
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default:
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llvm_unreachable("Opcode not supported");
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}
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}
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}
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}
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void IRTranslator::finalize() {
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void IRTranslator::finalize() {
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// Release the memory used by the different maps we
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// needed during the translation.
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ValToVRegs.clear();
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Constants.clear();
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}
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}
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IRTranslator::IRTranslator()
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IRTranslator::IRTranslator()
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}
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}
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bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
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bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
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const Function &F = *MF.getFunction();
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for (const BasicBlock &BB: F) {
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for (const Instruction &Inst: BB) {
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bool Succeeded = translate(Inst);
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if (!Succeeded) {
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DEBUG(dbgs() << "Cannot translate: " << Inst << '\n');
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report_fatal_error("Unable to translate instruction");
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}
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}
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}
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return false;
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return false;
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}
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}
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