forked from OSchip/llvm-project
[AArch64] Peephole rule to remove redundant cmp after cset.
Comparisons to zero or one after cset instructions can be safely removed in examples like: cset w9, eq cset w9, eq cmp w9, #1 ---> <removed> b.ne .L1 b.ne .L1 cset w9, eq cset w9, eq cmp w9, #0 ---> <removed> b.ne .L1 b.eq .L1 Peephole optimization to detect suitable cases and get rid of that comparisons added. Differential Revision: https://reviews.llvm.org/D98564
This commit is contained in:
Pavel Iliin
parent
d8805574c1
commit
2ec16103c6
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@ -1463,14 +1463,16 @@ bool AArch64InstrInfo::optimizeCompareInstr(
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// FIXME:CmpValue has already been converted to 0 or 1 in analyzeCompare
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// function.
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assert((CmpValue == 0 || CmpValue == 1) && "CmpValue must be 0 or 1!");
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if (CmpValue != 0 || SrcReg2 != 0)
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if (SrcReg2 != 0)
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return false;
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// CmpInstr is a Compare instruction if destination register is not used.
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if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
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return false;
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return substituteCmpToZero(CmpInstr, SrcReg, MRI);
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if (!CmpValue && substituteCmpToZero(CmpInstr, SrcReg, *MRI))
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return true;
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return removeCmpToZeroOrOne(CmpInstr, SrcReg, CmpValue, *MRI);
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}
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/// Get opcode of S version of Instr.
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@ -1524,13 +1526,44 @@ static unsigned sForm(MachineInstr &Instr) {
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}
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/// Check if AArch64::NZCV should be alive in successors of MBB.
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static bool areCFlagsAliveInSuccessors(MachineBasicBlock *MBB) {
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static bool areCFlagsAliveInSuccessors(const MachineBasicBlock *MBB) {
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for (auto *BB : MBB->successors())
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if (BB->isLiveIn(AArch64::NZCV))
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return true;
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return false;
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}
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/// \returns The condition code operand index for \p Instr if it is a branch
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/// or select and -1 otherwise.
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static int
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findCondCodeUseOperandIdxForBranchOrSelect(const MachineInstr &Instr) {
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switch (Instr.getOpcode()) {
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default:
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return -1;
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case AArch64::Bcc: {
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int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
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assert(Idx >= 2);
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return Idx - 2;
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}
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case AArch64::CSINVWr:
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case AArch64::CSINVXr:
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case AArch64::CSINCWr:
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case AArch64::CSINCXr:
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case AArch64::CSELWr:
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case AArch64::CSELXr:
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case AArch64::CSNEGWr:
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case AArch64::CSNEGXr:
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case AArch64::FCSELSrrr:
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case AArch64::FCSELDrrr: {
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int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
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assert(Idx >= 1);
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return Idx - 1;
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}
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}
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}
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namespace {
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struct UsedNZCV {
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@ -1556,31 +1589,10 @@ struct UsedNZCV {
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/// Returns AArch64CC::Invalid if either the instruction does not use condition
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/// codes or we don't optimize CmpInstr in the presence of such instructions.
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static AArch64CC::CondCode findCondCodeUsedByInstr(const MachineInstr &Instr) {
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switch (Instr.getOpcode()) {
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default:
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return AArch64CC::Invalid;
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case AArch64::Bcc: {
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int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
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assert(Idx >= 2);
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return static_cast<AArch64CC::CondCode>(Instr.getOperand(Idx - 2).getImm());
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}
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case AArch64::CSINVWr:
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case AArch64::CSINVXr:
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case AArch64::CSINCWr:
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case AArch64::CSINCXr:
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case AArch64::CSELWr:
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case AArch64::CSELXr:
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case AArch64::CSNEGWr:
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case AArch64::CSNEGXr:
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case AArch64::FCSELSrrr:
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case AArch64::FCSELDrrr: {
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int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV);
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assert(Idx >= 1);
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return static_cast<AArch64CC::CondCode>(Instr.getOperand(Idx - 1).getImm());
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}
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}
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int CCIdx = findCondCodeUseOperandIdxForBranchOrSelect(Instr);
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return CCIdx >= 0 ? static_cast<AArch64CC::CondCode>(
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Instr.getOperand(CCIdx).getImm())
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: AArch64CC::Invalid;
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}
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static UsedNZCV getUsedNZCV(AArch64CC::CondCode CC) {
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@ -1627,6 +1639,41 @@ static UsedNZCV getUsedNZCV(AArch64CC::CondCode CC) {
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return UsedFlags;
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}
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/// \returns Conditions flags used after \p CmpInstr in its MachineBB if they
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/// are not containing C or V flags and NZCV flags are not alive in successors
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/// of the same \p CmpInstr and \p MI parent. \returns None otherwise.
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///
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/// Collect instructions using that flags in \p CCUseInstrs if provided.
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static Optional<UsedNZCV>
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examineCFlagsUse(MachineInstr &MI, MachineInstr &CmpInstr,
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const TargetRegisterInfo &TRI,
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SmallVectorImpl<MachineInstr *> *CCUseInstrs = nullptr) {
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MachineBasicBlock *CmpParent = CmpInstr.getParent();
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if (MI.getParent() != CmpParent)
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return None;
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if (areCFlagsAliveInSuccessors(CmpParent))
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return None;
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UsedNZCV NZCVUsedAfterCmp;
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for (MachineInstr &Instr : instructionsWithoutDebug(
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std::next(CmpInstr.getIterator()), CmpParent->instr_end())) {
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if (Instr.readsRegister(AArch64::NZCV, &TRI)) {
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AArch64CC::CondCode CC = findCondCodeUsedByInstr(Instr);
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if (CC == AArch64CC::Invalid) // Unsupported conditional instruction
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return None;
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NZCVUsedAfterCmp |= getUsedNZCV(CC);
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if (CCUseInstrs)
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CCUseInstrs->push_back(&Instr);
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}
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if (Instr.modifiesRegister(AArch64::NZCV, &TRI))
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break;
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}
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if (NZCVUsedAfterCmp.C || NZCVUsedAfterCmp.V)
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return None;
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return NZCVUsedAfterCmp;
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}
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static bool isADDSRegImm(unsigned Opcode) {
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return Opcode == AArch64::ADDSWri || Opcode == AArch64::ADDSXri;
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}
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@ -1646,44 +1693,21 @@ static bool isSUBSRegImm(unsigned Opcode) {
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/// or if MI opcode is not the S form there must be neither defs of flags
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/// nor uses of flags between MI and CmpInstr.
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/// - and C/V flags are not used after CmpInstr
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static bool canInstrSubstituteCmpInstr(MachineInstr *MI, MachineInstr *CmpInstr,
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const TargetRegisterInfo *TRI) {
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assert(MI);
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assert(sForm(*MI) != AArch64::INSTRUCTION_LIST_END);
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assert(CmpInstr);
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static bool canInstrSubstituteCmpInstr(MachineInstr &MI, MachineInstr &CmpInstr,
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const TargetRegisterInfo &TRI) {
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assert(sForm(MI) != AArch64::INSTRUCTION_LIST_END);
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const unsigned CmpOpcode = CmpInstr->getOpcode();
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const unsigned CmpOpcode = CmpInstr.getOpcode();
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if (!isADDSRegImm(CmpOpcode) && !isSUBSRegImm(CmpOpcode))
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return false;
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if (MI->getParent() != CmpInstr->getParent())
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return false;
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if (areCFlagsAliveInSuccessors(CmpInstr->getParent()))
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if (!examineCFlagsUse(MI, CmpInstr, TRI))
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return false;
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AccessKind AccessToCheck = AK_Write;
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if (sForm(*MI) != MI->getOpcode())
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if (sForm(MI) != MI.getOpcode())
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AccessToCheck = AK_All;
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if (areCFlagsAccessedBetweenInstrs(MI, CmpInstr, TRI, AccessToCheck))
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return false;
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UsedNZCV NZCVUsedAfterCmp;
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for (const MachineInstr &Instr :
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instructionsWithoutDebug(std::next(CmpInstr->getIterator()),
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CmpInstr->getParent()->instr_end())) {
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if (Instr.readsRegister(AArch64::NZCV, TRI)) {
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AArch64CC::CondCode CC = findCondCodeUsedByInstr(Instr);
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if (CC == AArch64CC::Invalid) // Unsupported conditional instruction
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return false;
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NZCVUsedAfterCmp |= getUsedNZCV(CC);
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}
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if (Instr.modifiesRegister(AArch64::NZCV, TRI))
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break;
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}
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return !NZCVUsedAfterCmp.C && !NZCVUsedAfterCmp.V;
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return !areCFlagsAccessedBetweenInstrs(&MI, &CmpInstr, &TRI, AccessToCheck);
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}
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/// Substitute an instruction comparing to zero with another instruction
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@ -1692,20 +1716,19 @@ static bool canInstrSubstituteCmpInstr(MachineInstr *MI, MachineInstr *CmpInstr,
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/// Return true on success.
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bool AArch64InstrInfo::substituteCmpToZero(
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MachineInstr &CmpInstr, unsigned SrcReg,
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const MachineRegisterInfo *MRI) const {
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assert(MRI);
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const MachineRegisterInfo &MRI) const {
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// Get the unique definition of SrcReg.
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MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
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MachineInstr *MI = MRI.getUniqueVRegDef(SrcReg);
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if (!MI)
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return false;
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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const TargetRegisterInfo &TRI = getRegisterInfo();
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unsigned NewOpc = sForm(*MI);
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if (NewOpc == AArch64::INSTRUCTION_LIST_END)
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return false;
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if (!canInstrSubstituteCmpInstr(MI, &CmpInstr, TRI))
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if (!canInstrSubstituteCmpInstr(*MI, CmpInstr, TRI))
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return false;
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// Update the instruction to set NZCV.
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@ -1714,7 +1737,133 @@ bool AArch64InstrInfo::substituteCmpToZero(
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bool succeeded = UpdateOperandRegClass(*MI);
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(void)succeeded;
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assert(succeeded && "Some operands reg class are incompatible!");
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MI->addRegisterDefined(AArch64::NZCV, TRI);
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MI->addRegisterDefined(AArch64::NZCV, &TRI);
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return true;
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}
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/// \returns True if \p CmpInstr can be removed.
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///
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/// \p IsInvertCC is true if, after removing \p CmpInstr, condition
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/// codes used in \p CCUseInstrs must be inverted.
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static bool canCmpInstrBeRemoved(MachineInstr &MI, MachineInstr &CmpInstr,
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int CmpValue, const TargetRegisterInfo &TRI,
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SmallVectorImpl<MachineInstr *> &CCUseInstrs,
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bool &IsInvertCC) {
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assert((CmpValue == 0 || CmpValue == 1) &&
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"Only comparisons to 0 or 1 considered for removal!");
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// MI is 'CSINCWr %vreg, wzr, wzr, <cc>' or 'CSINCXr %vreg, xzr, xzr, <cc>'
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unsigned MIOpc = MI.getOpcode();
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if (MIOpc == AArch64::CSINCWr) {
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if (MI.getOperand(1).getReg() != AArch64::WZR ||
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MI.getOperand(2).getReg() != AArch64::WZR)
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return false;
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} else if (MIOpc == AArch64::CSINCXr) {
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if (MI.getOperand(1).getReg() != AArch64::XZR ||
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MI.getOperand(2).getReg() != AArch64::XZR)
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return false;
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} else {
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return false;
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}
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AArch64CC::CondCode MICC = findCondCodeUsedByInstr(MI);
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if (MICC == AArch64CC::Invalid)
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return false;
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// NZCV needs to be defined
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if (MI.findRegisterDefOperandIdx(AArch64::NZCV, true) != -1)
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return false;
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// CmpInstr is 'ADDS %vreg, 0' or 'SUBS %vreg, 0' or 'SUBS %vreg, 1'
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const unsigned CmpOpcode = CmpInstr.getOpcode();
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bool IsSubsRegImm = isSUBSRegImm(CmpOpcode);
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if (CmpValue && !IsSubsRegImm)
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return false;
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if (!CmpValue && !IsSubsRegImm && !isADDSRegImm(CmpOpcode))
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return false;
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// MI conditions allowed: eq, ne, mi, pl
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UsedNZCV MIUsedNZCV = getUsedNZCV(MICC);
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if (MIUsedNZCV.C || MIUsedNZCV.V)
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return false;
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Optional<UsedNZCV> NZCVUsedAfterCmp =
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examineCFlagsUse(MI, CmpInstr, TRI, &CCUseInstrs);
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// Condition flags are not used in CmpInstr basic block successors and only
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// Z or N flags allowed to be used after CmpInstr within its basic block
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if (!NZCVUsedAfterCmp)
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return false;
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// Z or N flag used after CmpInstr must correspond to the flag used in MI
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if ((MIUsedNZCV.Z && NZCVUsedAfterCmp->N) ||
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(MIUsedNZCV.N && NZCVUsedAfterCmp->Z))
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return false;
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// If CmpInstr is comparison to zero MI conditions are limited to eq, ne
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if (MIUsedNZCV.N && !CmpValue)
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return false;
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// There must be no defs of flags between MI and CmpInstr
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if (areCFlagsAccessedBetweenInstrs(&MI, &CmpInstr, &TRI, AK_Write))
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return false;
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// Condition code is inverted in the following cases:
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// 1. MI condition is ne; CmpInstr is 'ADDS %vreg, 0' or 'SUBS %vreg, 0'
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// 2. MI condition is eq, pl; CmpInstr is 'SUBS %vreg, 1'
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IsInvertCC = (CmpValue && (MICC == AArch64CC::EQ || MICC == AArch64CC::PL)) ||
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(!CmpValue && MICC == AArch64CC::NE);
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return true;
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}
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/// Remove comparision in csinc-cmp sequence
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///
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/// Examples:
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/// 1. \code
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/// csinc w9, wzr, wzr, ne
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/// cmp w9, #0
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/// b.eq
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/// \endcode
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/// to
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/// \code
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/// csinc w9, wzr, wzr, ne
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/// b.ne
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/// \endcode
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///
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/// 2. \code
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/// csinc x2, xzr, xzr, mi
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/// cmp x2, #1
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/// b.pl
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/// \endcode
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/// to
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/// \code
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/// csinc x2, xzr, xzr, mi
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/// b.pl
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/// \endcode
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///
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/// \param CmpInstr comparison instruction
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/// \return True when comparison removed
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bool AArch64InstrInfo::removeCmpToZeroOrOne(
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MachineInstr &CmpInstr, unsigned SrcReg, int CmpValue,
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const MachineRegisterInfo &MRI) const {
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MachineInstr *MI = MRI.getUniqueVRegDef(SrcReg);
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if (!MI)
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return false;
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const TargetRegisterInfo &TRI = getRegisterInfo();
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SmallVector<MachineInstr *, 4> CCUseInstrs;
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bool IsInvertCC = false;
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if (!canCmpInstrBeRemoved(*MI, CmpInstr, CmpValue, TRI, CCUseInstrs,
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IsInvertCC))
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return false;
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// Make transformation
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CmpInstr.eraseFromParent();
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if (IsInvertCC) {
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// Invert condition codes in CmpInstr CC users
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for (MachineInstr *CCUseInstr : CCUseInstrs) {
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int Idx = findCondCodeUseOperandIdxForBranchOrSelect(*CCUseInstr);
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assert(Idx >= 0 && "Unexpected instruction using CC.");
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MachineOperand &CCOperand = CCUseInstr->getOperand(Idx);
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AArch64CC::CondCode CCUse = AArch64CC::getInvertedCondCode(
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static_cast<AArch64CC::CondCode>(CCOperand.getImm()));
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CCOperand.setImm(CCUse);
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}
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}
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return true;
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}
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@ -334,7 +334,9 @@ private:
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MachineBasicBlock *TBB,
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ArrayRef<MachineOperand> Cond) const;
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bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
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const MachineRegisterInfo *MRI) const;
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const MachineRegisterInfo &MRI) const;
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bool removeCmpToZeroOrOne(MachineInstr &CmpInstr, unsigned SrcReg,
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int CmpValue, const MachineRegisterInfo &MRI) const;
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/// Returns an unused general-purpose register which can be used for
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/// constructing an outlined call if one exists. Returns 0 otherwise.
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@ -12,7 +12,6 @@ body: |
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; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
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; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr killed [[DEF]], [[COPY]], implicit-def $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32common = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri killed [[CSINCWr]], 1, 0, implicit-def $nzcv
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; CHECK: Bcc 1, %bb.2, implicit $nzcv
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; CHECK: B %bb.1
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; CHECK: bb.1:
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@ -51,8 +50,7 @@ body: |
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; CHECK: [[DEF:%[0-9]+]]:gpr64 = IMPLICIT_DEF
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; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr killed [[DEF]], [[COPY]], implicit-def $nzcv
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; CHECK: [[CSINCXr:%[0-9]+]]:gpr64common = CSINCXr $xzr, $xzr, 1, implicit $nzcv
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; CHECK: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri killed [[CSINCXr]], 0, 0, implicit-def $nzcv
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; CHECK: Bcc 0, %bb.2, implicit $nzcv
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; CHECK: Bcc 1, %bb.2, implicit $nzcv
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; CHECK: B %bb.1
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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@ -155,8 +153,7 @@ body: |
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $nzcv
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; CHECK: [[CSINCWr:%[0-9]+]]:gpr32common = CSINCWr $wzr, $wzr, 1, implicit $nzcv
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; CHECK: [[ADDSWri:%[0-9]+]]:gpr32 = ADDSWri killed [[CSINCWr]], 0, 0, implicit-def $nzcv
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; CHECK: Bcc 1, %bb.2, implicit $nzcv
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; CHECK: Bcc 0, %bb.2, implicit $nzcv
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; CHECK: B %bb.1
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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@ -254,8 +251,7 @@ body: |
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; CHECK: liveins: $nzcv
|
||||
; CHECK: [[CSINCWr:%[0-9]+]]:gpr32common = CSINCWr $wzr, $wzr, 5, implicit $nzcv
|
||||
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri killed [[CSINCWr]], 1, 0, implicit-def $nzcv
|
||||
; CHECK: Bcc 4, %bb.2, implicit $nzcv
|
||||
; CHECK: Bcc 5, %bb.2, implicit $nzcv
|
||||
; CHECK: B %bb.1
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.2(0x80000000)
|
||||
|
|
|
|||
|
|
@ -189,8 +189,6 @@ define half @test_select(half %a, half %b, i1 zeroext %c) #0 {
|
|||
; CHECK-CVT-DAG: fcvt s1, h1
|
||||
; CHECK-CVT-DAG: fcvt s0, h0
|
||||
; CHECK-CVT-DAG: fcmp s2, s3
|
||||
; CHECK-CVT-DAG: cset [[CC:w[0-9]+]], ne
|
||||
; CHECK-CVT-DAG: cmp [[CC]], #0
|
||||
; CHECK-CVT-NEXT: fcsel s0, s0, s1, ne
|
||||
; CHECK-CVT-NEXT: fcvt h0, s0
|
||||
; CHECK-CVT-NEXT: ret
|
||||
|
|
@ -228,8 +226,6 @@ define float @test_select_cc_f32_f16(float %a, float %b, half %c, half %d) #0 {
|
|||
; CHECK-CVT-DAG: fcvt s0, h0
|
||||
; CHECK-CVT-DAG: fcvt s1, h1
|
||||
; CHECK-CVT-DAG: fcmp s2, s3
|
||||
; CHECK-CVT-DAG: cset w8, ne
|
||||
; CHECK-CVT-NEXT: cmp w8, #0
|
||||
; CHECK-CVT-NEXT: fcsel s0, s0, s1, ne
|
||||
; CHECK-CVT-NEXT: fcvt h0, s0
|
||||
; CHECK-CVT-NEXT: ret
|
||||
|
|
|
|||
Loading…
Reference in New Issue