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AMDGPU/GlobalISel: Add some more tests for add3 folding 

These currently fail to form add3 due to the pointer type, but they
should be handle.
This commit is contained in:
Matt Arsenault 2020-03-24 14:26:23 -04:00 committed by Matt Arsenault
parent 26ebc51a34
commit 2ea4605105
1 changed files with 87 additions and 0 deletions
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87
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
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@ -130,3 +130,90 @@ body: |
S_ENDPGM 0, implicit %4, implicit %3
...
---
name: add_p3_vgpr_vgpr_vgpr
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: add_p3_vgpr_vgpr_vgpr
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX8: %4:vgpr_32, dead %5:sreg_64_xexec = V_ADD_I32_e64 %3, [[COPY2]], 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit %4
; GFX9-LABEL: name: add_p3_vgpr_vgpr_vgpr
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
; GFX10-LABEL: name: add_p3_vgpr_vgpr_vgpr
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX10: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
%0:vgpr(p3) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
%3:vgpr(p3) = G_PTR_ADD %0, %1
%4:vgpr(p3) = G_PTR_ADD %3, %2
S_ENDPGM 0, implicit %4
...
---
name: add_p5_vgpr_vgpr_vgpr
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: add_p5_vgpr_vgpr_vgpr
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX8: %4:vgpr_32, dead %5:sreg_64_xexec = V_ADD_I32_e64 %3, [[COPY2]], 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit %4
; GFX9-LABEL: name: add_p5_vgpr_vgpr_vgpr
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
; GFX10-LABEL: name: add_p5_vgpr_vgpr_vgpr
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX10: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
%0:vgpr(p5) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
%3:vgpr(p5) = G_PTR_ADD %0, %1
%4:vgpr(p5) = G_PTR_ADD %3, %2
S_ENDPGM 0, implicit %4
...